write analog data in timed loop FPGA

[TRanjith]

Hi,

I have array of data in FIFO from RT VI. I have to read the array of data in FPGA and write the data to Analog channel with 20us time interval. I have to write the same data back to another FIFO. When i use AO control in timed loop, i got compilation errorsaying that i cant use it in timed loop. how do i achive this?

Thank you,

Ranjith

[AdnanZ]

Timed Loops in LabVIEW FPGA are known as Single Cycle Timed Loops. When used with an FPGA target this loop executes all functions inside within one tick of the FPGA clock you have selected. Functions that take longer than one tick, such as analog I/O functions or any functions that wait cannot be used inside the SCTL. Also, if you have a chain of logic inside the loop that takes longer than one clock tick to execute, this logic cannot be used inside the SCTL and your VI will fail to compile.

Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module

So, to answer your question, just use a while loop instead.

[JK1]

SCTL [single cycle timed loops] in FPGA executes all the code within in 1 clock cycle of the FPGA base clock.  A analog write cannot be completed within this short period and hence analog rw operation cannot be performed in SCTL.

Use while loop to perform analog rw operations.

[TRanjith]

I am trying to acheive  this using while loop with ticks timer. if the diference is >=20 us, i shall execute the code. Will this be reliable? are there any other better ways to do it? how much time does FIFO read and FIFO write takes?

[AdnanZ]

FPGAs are definitely reliable. Try to benchmark the FIFO reads and writes yourself.