@GerdW wrote:
Hi Ambrose,
why use SCTL at all?
Why use (while) loops inside the case structure?
Why do you read the DIO pins outside of your loop?
I just correct my vi. miss use the SCTL.
The reason i use while loop inside the case structure (only false case this case is count down) is because I doing X1 decoding and every falling edge of the signal A the counter will count down.
I just make correction for DIO pin to put inside the loop d. Do you have an idea how to make this while loop inside case structure to implement on fpga? Since i need to reduce resource use of fpga. Thank you.
