I get the Timing Violations error when compiling an acquisition using the NI 9205 module on my NI 9149.
I have tried compiling on the 40, 80 and 120MHz clocks with same results. I am not performing any complex tasks as yet so why am I getting this issue.
When I compile same on my cRIO, it compiles fine with no issues
I have copied the timing violations details here and theFPGA file
Path 1
This non-diagram component is required in the design. Internal name: /Crio9233Resource3/Crio9233ResourceCorex/Crio9233x/Crio9233AdcSyncHandlerx/cSync_n_reg.
This non-diagram component is required in the design. Internal name: /dio25_INST_0/O.
Path 2
This non-diagram component is required in the design. Internal name: /cRio9205_Resource2/Crio9205ResourceCorex/cRio9205x/cRio9205CommSmx/cShiftReg_reg[15].
This non-diagram component is required in the design. Internal name: /dio13_INST_0/O.