reading data off two FIFOs in host vi

[kwaris]

Hi,

I have two FIFOs hi speed and lo speed which are transferrring analog and hi speed digital data from FPGA to host vi. I have just finished calling HI speed FIFO and writing the data into binary by using decimate, build array and transpose function.

Now in order to get data off both analog and digital module at the same time, would it be ok to just create another chain of calling lo speed DMA by connecting the reference and error wires in parallel to open reference function?? Or there's a better way!

Many thanks for help in advance!

Best regards

[mishkin]

Kwaris,

Yes, that should be just fine. You will probably end up having two loops, one reading the high speed DMA FIFO and one reading the slower FIFO. You'll also want to synchronize the DMA transfers somehow. There are examples of Host synchronization in the example finder, and you can also read through this one: What is the Best Method For Synchronizing a LabVIEW FPGA and a Host Interface VI?

Cheers,