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"starter placer cost table" option in FPGA

Can someone explain when to use the "starter placer cost table" option in FPGA?



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For others reading this, here's what we're talking about:

Placer Cost Table.PNG


Here's what the Xilinx Documentation says about it (it's a map & place and route feature):

Starting Placer Cost Table (1-100) 

Specifies a placement initialization value with which to begin the Place and Route attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value. Select a number from 1 to 100. The number you choose corresponds to a cost table index and results in different Place and Route strategies. Cost tables assign weighted values to relevant factors such as constraints specified in the input file (for example, certain components must be in certain locations), the length of connections, and the available routing resources. Cost-based placement is described in the "PAR" chapter of the Command Line Tools User Guide.
By default, this property is set to 1.

Basically, it's the starting seed for the Xilinx Algorithms that try to get all of your logic in the right place on the FPGA.


So, back to your question: when should you change it? I would say almost never. I think the best time to use it is if you're running into a PAR bug that causes the compilation to hang or crash. It can help you meet timing, but you're likely going to have to do a lot (hundreds) of compilations to find the right value. Since we only let you use a random value... hitting that checkbox might let you meet timing when you compile, and then not the next time. Useful if you're tight on timing and have a final design that you're trying to get a bitfile for. Not so useful during development.


Here's a full article on Xilinx's website:



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I'm trying to solve my issue I posted here.  I already tried compiling though with the option checked and still had Timing Errors.



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