pxi 7852r

[efriday4455]

Hi,

I currently have a PXI 7852r, and I am trying to get the data from the FPGA card to the post processing vi.  I wrote a simple loop to grab the data from the fpga, but when I pass it to the host vi I start to get varying time.  For example, I tell the card to wait 50 usec between samples and it does but when I run the host vi my timing goes haywire.  I guess what I'm asking is how do I get the data from the card sampled at 50 usec to the post processing stage.

Any help would be appreciated,

[X.]

It would be helpful, in order to be of any help, to show what you are currently doing...

Anyhow, here are a few pointers that may be helpful (or not):

To communicate with an FPGA in a deterministic manner (without loosing data), you need to use a target- to-host FIFO on your FPGA. Then allocate enough memory on your PC to buffer the data transfered from the FPGA by DMA. Then read your target-to-host FIFO on a regular basis on the PC side to empy it and avoid it filling up.

On the FPGA side, you need to use timed-loop at the desired frequency to read you data and push the data into the transfer FIFO. You may need an intermediate local FIFO to buffer the data stream (for instance if you read several lines at once, you may only be able to push one or two into the FIFO within the timed-loop period, although at 50 us per loop, that should really not be a problem).

The concept of DMA FIFO is described in the Example "DMA Buffered Acquisition - R Series"

The concept of local FIFO is described in the Example "FIFO communication between Timed Loops - R series".

[efriday4455]

Thank you for the reply and I shall look into it.  I am not an FPGA programmer and somehow got sucked in on this one.  All I really need is to sample the 8 Analog in for 18 secs at 50 usec a piece.

[X. · Accepted solution]

The first example I mentioned above does not use a timed loop, but you should probably be able to replace the while loop by a timed loop, set the clock to 200 kHz and still compile fine.

Depending on whether you want to trigger or not your acquisition, the host side of the VI might need to be slightly modified, but the provided VI should be a good starting point.

Post your VIs if you encounter some unexpected problems (or better yet, the project, as in the example, since there are a few FPGA definitions which won't come along if you just post the VIs).