putting the analog input/output icon in timed loop in FPGA VI

[TCPIP]

  I am using LabVIEW 8.2 with cRIO 9004 with the slots, I cannot putting the analog input/output in the timed loop in the FPGA VI and it raise errors when compiled.

Is it related to the software or hardware problem?

Does the new LabVIEW 8.5 solved the problems mentioned above?

[Christian Mergl]

Hey,

Maybe you can explain your problem a little bit more detailed, e.g. what exactly is this analog input/output, do you ment FPGA I/O Nodes?

Christian

[Christian_L]

The Timed Loop within a LabVIEW FPGA VI is a Single Cycle Timed Loop (SCTL). This loop is different from a timed loop used in LabVIEW for Windows or Real-Time.

The SCTL and all of its content executes in a single clock cycle of the FPGA. Therefore some functions and VIs can not be used inside of a SCTL as they require more than one FPGA clock cycle. Analog I/O functions in cRIO are not supported in the SCTL for this reason.

Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module

[Riccardo_97]

Buongiorno Christian, scusa se ti disturbo, volevo chiederti come si potesse fare per acquisire un segnale analogico con FPGA con una frequenza diversa da quella nominale, dato che non posso inserirlo dentro al SCTL.

Io ho provato a farlo con il procedimento nella foto, ma non so se sia corretto, perché in questo caso il modulo analogico estrae un valore ogni volta che il while loop si ripete e quindi con una frequenza diversa da quella dell'SCTL.

Grazie in anticipo per la risposta e buona giornata.

[GerdW]

Hi Riccardo,

what do you want to achieve with this SCTL in your code?

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@Riccardo_97 wrote:

I wanted to ask you how it could be done to acquire an analog signal with FPGA with a different frequency from the nominal one, since I cannot insert it inside the SCTL.

I tried to do it with the procedure in the photo, but I don't know if it is correct, because in this case the analog module extracts a value every time the while loop repeats and therefore with a different frequency from that of the SCTL.

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To set a certain iteration speed of the outer while loop you can simply place a Wait function into the loop! Either choose "ticks" or "µs" to set higher frequencies…

(It's most often recommended to also place a flat sequence, with the wait in the first frame and the AI node in the 2nd frame, to ensure proper timing.)

Btw. did you notice you are posting in a 13½ year old thread? Most often it makes sense to start a new thread after that long time…

[Riccardo_97]

Grazie per aver risposto alla mia domanda.

Volevo utilizzare un SCTL per avere prestazioni migliori, ma se non è il metodo più adatto inseririò un timed loop express VI come mi hai consigliato.

Ti chiedo scusa per aver commentato un post di tanto tempo fa, purtroppo non me ne sono accorto.

Ti ringrazio ancora per l'aiuto e ti auguro una piacevole giornata.

[GerdW]

Hi Riccardo,

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@Riccardo_97 wrote:

I wanted to use a SCTL for better performance, but if it is not the most suitable method I will insert a timed loop express VI as you advised me.

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You can improve FPGA behaviour with SCTLs, like using less fabric. It may even help to improve code performance, but: is this needed in your VI?

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@Riccardo_97 wrote:

I apologize for commenting on a post from a long time ago, unfortunately I didn't notice.

I thank you again for your help and I wish you a pleasant day.

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You also seem not to recognize you are writing in an English speaking forum. (There's also an Italian regional board…)

Bouna sera!

(Ti auguro una fantastica partita di calcio...)