punctured viterbi decoding using Xilinx IP core for LAbview FPGA 2014

[incisive]

HI

I want to apply viterbi decoding to my 3/4 punctured stream using xilinx IP core for labview fpga.

I read that for punctured of viterbi decoder v.7, depuncturing has to be external. Is there a code for depuncturing available?

What is the purpose of erasure flag?

I have to first append zeros in places where punturing is done?

How should I set the rate? Is there a design example available for hard coded 3/4 punctured viterbi decoder. Constraint length 7. If so please share. 

[Wan-L]

Hello Incisive,

Can you provide the document that you saw explaining how to configure the viterbi decoder. If you are questions regarding how to use a third party IP core, it is recommended that you contact the support channels of the third party. However, if you have questions regarding the LabVIEW FPGA environment or integrating IP cores in general, we can help you address them.