polynomial help required on FPGA!! please-

[srm@viewpointusa.com]

attached is a 8.6.1 fixed point implementation of what I think is your polynomial.  it runs in 4 clock ticks.  however, it takes 16 out of 40 multipliers on the cRIO target FPGA.  I don't know what else you have targeted for the FPGA, but this can be coded to reduce the number of multipliers.  You should note the configuration of each of the multipliers, specifically the limiting of the output resolution so that downstream operations do not get out of control.  NOTE: this implementation is rather specicific to this poly.  it is not coded for any set of coeffs.  NOTE: you should check the output against a high level implmentation of your algorithm to check for correcness and error.

Message Edited by stu@viewpointusa.com on 03-29-2009 06:34 PM

[WillD]

I think more information is required to properly optimize this problem.

Does the encoder count as integer?  You could increment it by a fixed value of 0.002222222 instead of 1 and get rid of the division, possibly.

Some known inputs and expected outputs would be useful for a proper implementation.

Really, what is the goal of this algorithm and overall use?

More high level information, if possible, about your application would be very useful.