parallel using of 1 digital line as both output and input

[Laurent80]

Hello,

I have the following problem:

I have a LabVIEW FPGA program that generates a incremental signal (with variable period and pulse width) on some digital output. As I want to count the generated pulses, I implemented in parallel a counter (UpDownCtr, SW Dir.vi - from the examples library) that reads directly the same digital line, using a Single-Cycle Timed Loop.

First I observed that my program was for example generating 9 pulses, and counting 11. Then I replaced the SCTL by a classic while Loop, but it still doesn't count properly; the only difference is, sometimes I have 10 pulses generated (instead of 9) for 11 counted.

Does someone know how to solve this problem ?

I thought about arbitration, but it is not possible to use it with digital input.

Would it be better to use some local variables ?

Or how can I synchronize both operations ?

Thanks in advance for the help,

Laurent

[Laurent80]

Hello again,

I solved my problem, and it had nothing to do with what I described :o). In fact, because of a division by zero, my program was first generating each time 2 very short pulses (few ns; that's why I didn't see them with my scope), and then the expected increments. The counter was fast enough to detect the 2 small pulses, which explains the offset...

anyway, ITEM CLOSED 🐵

Laurent