Dear all,
I would like to output to my NI6585 Adapter Module for NI FlexRio of 32 channels 200MHz Digital I/O, one word of 32bits every clock cycle in my FPGA module. I have done it before with DAQ, but never in FPGA and I am not able to do it.
First, I am dividing my file into some portions to send that data to 16 DMA FIFOs (I know that is the limit of my card). I am linking one fifo writting to the entrance of the other to write and read secuentially in the FPGA FIFOs and get the data correctly ordered. The main thing is that I want to output one word of 32 bits to my Adapter every clock cycle of 100MHz to read each bit from each channel pin.
I have thought to only destiny 15 FIFOs to the data and the last one to put it in order, like another fifo insede the FPGA, but how only outputting 32bits is possible with out a queue or so on?My data element is U8, but I should need the first 32 instead of the 8 ones... I really need a hand.
Thank you in advance. Here are two pictures of my VIs, if more information is need tell me, please.
Best regards,
Miguel.
