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myRIO FPGA bug where Loop Rate in millions while generating Sine Wave



I am writing a program to generate a Sine Wave and return its frequency so that I may use it. However, despite the Sine Wave being returned fine (I think) through a Target to Host FIFO (and read fine on the RT), running the FPGA by itself gives me a strange bug where the loop rate is around 20 ticks immediately after compilation, but in the millions on following runs. Also, as the vi is running for the first time, the iteration counter goes up to 1000+, but the iteration counter remains at 0 for later runs.


Would it be alright for someone to look through my code and see if something stands out that may be causing this? I have attached my project below.


As a note, I am trying to calculate the frequency of the generated sine wave by recording the time that the sine wave value is at 0 (technically, -0.01 < val < 0.01), and then finding the difference of this with the previous time that it was at 0. My logic here is that this difference in time would be 1/2 of a period, and then I could multiply its value by 2, then take the reciprocal to give me the frequency of the generated signal. This may not be a valid way to do this, so if anyone has tips on how to calculate the frequency of a signal purely on the FPGA (no RT), then let me know.


Picture of suspiciously high loop rate:




FPGA Target:

(this vi is under the "SineCreator" virtual folder)


FPGA Host:

(I doubt that this vi is necessary for solving the issue that I stated above, but someone may like to view it. This vi is under the "RT for AdcToDac" virtual folder)


- Best regards, 2001J

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