multiple timed loops in RT interface- initialization, communication

[Parikshit_Mehta]

Problem Description :
I am attempting to deploy an adaptive control system using cRIO. I have an NI
9505 that controls a motor, and triggers other part of the machine to produce
data. I get data in my control loop and perform on-line estimation (currently)
using RLS estimator.

I have two-fold trouble
1> My Motor control and data acquisition is on one FPGA VIs and data filtering  
and Estimation algorthon is on the other FPGA VI. I am supposed to call both of
the FPGAs in my RT interface VI with necessary operations.
Problem 1: How to simultaneously call two FPGA VIs in separate timed/while
loops in my interface VI?
2> Note that these two loops are supposed to talk with each other, once
estimation VI produces new coefficients, they are to be fed back to control VI,
I am not sure how to perform this.

It's kind of time critical that I accomplish this , Please help.

Thanks,

NI Software :  LabVIEW Professional Development System  version
NI Hardware :  CompactRIO device 

[_Tim]

Because of the nature of FPGA, you can’t call two FPGA VIs at the same time. When you call an FPGA VI, you load up an FPGA bit file and physically reconfigure the FPGA chip. The FPGA chip can only be configured for one bit file at a time, so simultaneously calling two files at once will not be possible. If you need to perform functions from both VIs simultaneously, you could try combining them into one master VI that contains the functionality of both VIs. You could then pass information to and from each RT loop to the appropriate section of FPGA code. Keep in mind that FPGAs are a finite resource, so you’ll need to make sure that this new larger FPGA VI still fits on your chip.

Hope this helps answer your questions!