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multiple fpga vi's with same interface, single RT vi

Hi everybody,
I'm using a crio system to control as experimental setup. In this setup several types of tests can be done and for each, basically the same control is done, but the returned data is different. Therefore i wrote several fpga vi's with the same controls on the interface, and a DMA fifo to transfer the data. I've also written a subvi for my RT system which reads the data from the DMA fifo and transfers it further downstream for analysis. This RT vi has to be rewritten for each FPGA vi as the FPGA vi references are incompatible. How do i make the subvi generic for all these FPGA vi's? The DMA fifo is the same, as is the type and amount of data...

looking forward to your suggestions,
Daniel Lindenaar
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Hello Daniel!

 

I am not sure which FPGA target you are currently using but one method to achieve what you want it to use the Up Cast method. If you use cRIO you have an example called ‘Using the Upcast Function - cRIO.lvproj’ and if you use R-Series look at the example called ‘Using the Upcast Function - R Series.lvproj’. Hope this helps and Merry Christmas!

Regards,
Jimmie Adolph
Systems Engineering Manager, National Instruments Northern European Region

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It's been a while, but i'm again confronted with the same problem...

The up-cast function won't work (at least according to the labview documentation) as i'm using DMA FIFO's

http://zone.ni.com/reference/en-XX/help/371599A-01/lvfpgahost/up_cast/ : "You cannot use this function with DMA FIFOs."

any other ideas, or an idea how to work around this?

thanks


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Hi Daniel,
 
The only option I can think of then is to use the same Reference for all VI's and use some generic way of sending settings to your target. For example you could place a boolean and a U32 on the front panel en use the U32 to sent and/or recieve configuration data between Host and FPGA and the boolean for handschaking. This way you could create a generic interface with FPGA and still be able to doe arbitrary configurations and use a DMA FIFO.
 
I'm not sure if this will work, I've not tried it before. The only problem I could think of would be if the registers coupled to the frontpanel objects would move between FPGA compiles. Then this would only work with one bitstream and not with the others. If they don't this could be a workaround.
 
Hope this helps.
 
Thanks
Karsten
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