LabVIEW
logical shift in FPGA
I just want to know which code will take fewer resources. In code1, we are using 2logical shifts with boolean OR. Both codes are the same in logic.
In the 2nd code, we are using 1 logical shift with 2 negates.
If you want to know such things the only sure way is to test it. Build both variants, copy and paste several times to get a potentially bigger difference, compile each and look at the number of used resources. And be aware that these results are specific to your setup (FPGA type and compiler version). They could be different on a different FPGA platform and/or compiler version.
Also to think about, are you sure you are not busy with premature optimizations? Not wanting to waste resources is a good idea, but spending hours or days to save a few gates in your design only makes sense when you are resource constrained, either by barely fitting into the available fabric or your logic causing timing violations. Otherwise it is spending lots of time and money on pretty looking things and some fuzzy feelings of being very smart. 😀
