I created a simple RC-(CR)2 IIR filter using DFD toolkit, and using “DFD fpga code generator.vi“, I generated a filter core to be used in my fpga vi. My problem is that the generated core is too slow for my fpga application. I found that the ratio of ”the sample frequency/fpga clock“ returned by the code generator vi is about 0.1. This means that the throughout for my 60 MHz fpga clock is 6 MHz, which is too much lower for my fpga application. Are there simple ways to increase the sample frequency that the filter core can handle?
I tried with several filter structures without much improvement in throughput. I know that the throughput of FIR filter can increase by means of using more pipelines stages.