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iir filter implementation in labview fpga

Hi, 

 

I created a simple RC-(CR)2 IIR filter using DFD toolkit, and using “DFD fpga code generator.vi“, I generated a filter core to be used in my fpga vi. My problem is that the generated core is too slow for my fpga application. I found that the ratio of ”the sample frequency/fpga clock“ returned by the code generator vi is  about 0.1. This means that the throughout for my 60 MHz fpga clock is 6 MHz, which is too much lower for my fpga application. Are there simple ways to increase the sample frequency that the filter core can handle?

 

I tried with several filter structures without much improvement in throughput. I know that the throughput of FIR filter can increase by means of using more pipelines stages.

 

What about the IIR filter?

 

 

Thank you in advance.

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You could try using the Xilinx IP: http://zone.ni.com/reference/en-XX/help/371599M-01/lvfpgahelp/fpga_xilinxip_descriptions/

 

They can go faster.


Certified LabVIEW Architect, Certified Professional Instructor, LabVIEW FPGA expert
ALE Consultants
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