how do i know if my fpga vi timing before i compile

[suni]

Hi,

Is there way to know that my FPGA VI is not going to give me a timing violation before i compile the code?

[Wiebe@CARYA]

"suni" <x@no.email> wrote in message
news:1235763607720-862051@exchange.ni.com...
> Hi,&nbsp;Is there way to know that my FPGA VI is not going to give me a
timing violation before i compile the code?

No.

Well, once you've seen all the timing violations, you will learn to make
estimates. That's all. THere is no way of telling this for LabVIEW either.
The only way for the LabVIEW to know if it will fit, is to actually compile,
optimize, and see if it will fit...

Regards,

Wiebe.

[DanRichards]

Hi,

There actually are some little-known problems that you can try to avoid that will prevent timing violations.

1. If you are using the old fixed-point (FXP) math VI's within a single-cycle timed loop (SCTL), you have options when double-clicking the VI's to pipeline the data through multiple iterations of the FPGA clock. If you don't set the right setting, you'll get a timing violation.

2. In general, if you use FXP data in a SCTL, a good idea would be to make sure that it is 32-bit or less. Otherwise, timing errors.

3. Keep your code efficient and pipeline data.

Hope this helps,

[Wiebe@CARYA]

Also, the clock frequency of the FPGA has great impact on this. With a
higher the frequency, less code will fit in a SCTL.

You'll get timing errors for sure if you use a sub vi in a SCTL, that is
reentrant and also used outside a SCTL. Can't see why this can't be avoided,
but it happens...

You can also devide the pipeline inside a SCTL with the use of shift
registers. You'll get a latency, but at least it's deterministic and fast.

Regards,

Wiebe.