how can I integrate customized IP core into PXIe-6592R?

[Jay.Gao]

Hi There,

PXIe-6592R

Question:

What exactly are the steps to integrate customized IP core into PXIe-6592R?

I have read the link here: 

http://digital.ni.com/public.nsf/allkb/723fe910af2d01a686257d89007702c4

from which says "It will also involve understanding the FPGA interface provided by the 6591R/92R and being able to appropriately interface those signals to the IP core and the wrapper.
Refer to a premade Sample Project to gain a better understanding of what is required in a CLIP."

Once you created a 6592R project, you can see the CLIP socket, but how I can know the requirements of this socket? Where are the signal definitions?

I have also read the example project (Aurrora), that one runs well, so I opened the source files (.VHD, .EDF ETC) inside the VHD files, there are lots of signals which I couldn't find the source? How the VHD file mapping the FPGA output to the 6592R port?

Is it OK to just simply copy the code?

Any help is highly appreciated!

Cheers,

Jay

[Jay.Gao]

Can any AE in Austin please help on this issue?

Thx

Jay

[Daniel.Parrott]

Hi Jay,

I would take a look through this white paper which I think better explains the process of both creating a CLIP and using the IP Integration node. 

Importing External IP into LabVIEW FPGA: https://knowledge.ni.com/KnowledgeArticleDetails?id=kA03q000000x0jiCAA&l=en-US

[Jay.Gao]

Thanks Parrot.

It's been long time since last time I logged into this forum. 🙂

Problem solved by non-Labview knowledge actually. To be honest the docs provided by NI and the so-called white paper both are kind of... well, how to say --- it's just like you couldn't scratch the point where itch on your back. LOL, 

Cheers,