how are resets generated in LabVIEW for FlexRIO

[JJMontante]

All,

My background is VHDL and Verilog implementations for ASIC and FPGA.  I assume that LabVIEW has at some point, a single synchronous reset to all of its logic.  I am creating a design that will be instantiating sections of VHDL IP, via IP Integration Nodes. While writing up my spec, I need to describe how a reset is propagated to all the flops in the design which will be peer reviewed for correctness of results. I need to understand exactly how LabVIEW handles resets to other clock domains.

A simple case would be this:  I have an external 50 MHz source synchronous data interface, and will be some limited processing of the data in that 50 MHz domain using an IP integration node. This IP is designed to have flops reset synchronous to the 50 MHz clock.

Separately, I have my the bulk of my processing and storage to host (via DMA FIFO) in a 100 MHz clock domain derived from the 40 MHz base clock. I will be transferring data from 50 MHz to 100 MHz using a FIFO.  This processing in 100 MHz contains flops that are reset synchronously to the 100 MHz domain.

From this scenario, you see that I have two clock domains with synchronous resets.  I need to understand how LabVIEW FPGA creates the reset signals that are inputs to my IP integration nodes, in order to understand whether I need to incorporate any reset synchronization circuits within my VHDL.

Thanks for any help, and if you require any further details or context, please let me know and I will fill in additional details.

-Jim

[T-REX$]

Hey Jim,

There are really 2 resets we could be dealing with here.

1. A reset signal in your IP's top level port map

2. The 'IP Reset' signal in the IPIN configuration window

If you're talking about a boolean reset signal that you're wiring into your IP, then the synchronization would have to be done on the block diagram of your VI or in your VHDL.

If you're talking about option 2, then that's actually an asynchronous reset signal.

So I guess let's start off with which signal you're referring to...

[JJMontante]

Thanks for the reply.  I am asking about the reset that Labview provides to your VHDL IP in each clock domain.  I'm trying to understand if the resest that labview is providing to the IP (that would wire into my IP's port-map reset) has been synchronized into the clock domain in which my IP Integration node operates.  Specifically, if I have two single-cycle-timed-loops, does each timed loop have its own reset that is synchronized into that timed loop clock domain (in this case, I would not need to add a reset synchronizer into this design).  Or perhaps is labview providing a global reset signal which may be asynchronous to my SCTL domains (in this case, I would need to put a synchronizer in my IP).

-J

[T-REX$ · Accepted solution]

Hey Jim,

So, option 2 then... in that case, you're looking at an asynchronous reset signal and should account for it in your VHDL similarly to the following to ensure that your resets are asserted synchronously.

[JJMontante]

TJ - thanks for the info, that's exactly the detail I needed to move forward.

-J