LabVIEW
fpga
Hi there FPGAcode,
Welcome to the NI Forums!
"I tried to use Local and Global Variable but I found it is lossy."
- Firstly, this depends on what the actual application is doing. For example, if you're discussing the transfer of data across one area of the FPGA from another, then a local variable will not be lossy as it is an explicit circuit connection being made in hardware; the same value will propogate through within one clock cycle. However, the implications of this form of data communication vary depending on the application.
Often it is useful to set up a communication buffer if the data that is being passed has lengthy operations performed on it that take multiple clock cycles, such as through the use of a hardware divider. If you are communicating from an FPGA through to a Real Time System, then you are correct in saying that without a Direct Memory Access FIFO communication would be lossy because the rate at which an OS can communicate is at a much lower rate than the FPGA can run; therefore it's important to setup a data communication channel as suitable for your application as possible. If you're finding this channel of communication lossy, I would suggest reading more elements from the FIFO and at a faster rate.
"System occupy 97.5% of FPGA resource"
- That's impressive! I've never seen an application which takes up nearly an entire FPGA. I would love to take a look!
"I have used many VHDL function block because Ni Labview function doesn't support many Operation (Found more latency) and also found NI Function occupy more resource then function written in VHDL."
- Which functions have you found that are missing? I've done a lot of work in VHDL and I've found that LabVIEW is just as capable for implementing Hardware Description, except it definitely doesn't give me as many headaches!
"Can anyone please Guide me What is the best way or any other way , to transfer Single Bit (Boolean) data between Two parallel Loop running on same Clock rate?"
- As long as these two parallel While Loops are running on the FPGA, then I'd recommend the use of a Local Variable; promise! A local variable will be a direct route between two areas of circuitry; remember the programs we write are describing hardware, so we need to think differently. Everything we write becomes a hardware based configuration. It can be a little confusing at first, especially if you're used to conventional LabVIEW programming.
I would suggest to benchmark your application, you read the outputs of the Timed Out? terminals of the FIFO nodes in order to accurately confirm whether we're incorrectly reading from the buffer.
If our reading and writing process is configured properly, the DMA FIFOs shouldn't be losing any information. I'd recommend looking at the amount of data you're actually writing to these channels and confirming whether we're reading fast enough.
I hope this helps!
Hi FPGAcode!
With DMA FIFOs, you would not lose any data if the Read and Write processes were configured so that data was not being read too quickly or too slowly; it is because of DMA FIFOs that we can remove any coupling between deterministic and non-deterministic loops in software.
In terms of FIFO 'latency', I can think of the inherent delay of these devices in two ways:
Propogation Logic Delay - This type of delay is inescapable with FPGAs as it is referred to as the amount of time taken for logic elements to settle in particular states. In this case, this means the amount of time for particular FIFO circuitry to complete their operation. I'm unsure of the exact delay of actual FIFO operation, however it will be in the nanosecond region and should be unnoticeable with respect to the driving clock.
Number of Elements Delay - This type of delay occurs with respect to just how many elements need attention in the FIFO before it reaches the element of data which we're benchmarking latency from. This will be the biggest source of any latency that you notice in your application.
Have you managed to make use of Front Panel indicators to warn you of any FIFO occurence of overflow?
We could use these to fine tune your FIFO setup to ensure data is propogated effectively without any loss.
80MHz SCTL - The maximum clock rate of the Virtex 5 FPGA on board the NI 7962R is 500MHz.This would imply that via the implementation of an SCTL, we would be able to run at a 500MHz rate. However, because you are receiving timing violation errors, I would imagine that this is due to the logic propogation delays inherent in the use of FFT functions due to the size of logic required for implementation; this is entirely dependant on the configuration of the FFT in terms of Bit Width and Word Length. When making use of the FFT Function, you are shown the Configure FFT Window which tells you directly the latency in its operation; you can make use of this information to confirm whether or not it would successfully operate under a particular clock frequency.
Signal Simulation - There are no timing diagrams built into LabVIEW FPGA, however even through LabVIEW FPGA we can make use of the standard debugging tools such as Highlight Execution and Probes in order to affirm correct operation of developed hardware code. By knowing how fast particular loops operate, from this we need only look at Front Panel Indicators to see if the data itself is as expected. If you wanted to see the signals produced, you could use a high speed digitizer on the pins.
I hope this helps.
