fpga

[FEUP_Researcher]

Hello,

I am developing an application for acquire various signals sensors using cRIO 9072 and the modules 9205, 9211, 9237, 9233 and 9401. My doubts are regarding to the way how I implement the DMA FIFOS in the FPGA and RT. Once I have different modules with different ADC's, I'm using more than one DMA FIFO. For this case, should I use more than one DMA FIFO to pass data from the Target to the Host, or should I use the option DMA FIFO (Target-to-Scoped) for passing data between FPGA while loops and than use only one DMA FIFO (Target-to-Host) to pass to the Host all the data?

And here (in RT), if I'm using various DMA FIFOS (target-to-Host) should I put the different FIFO's read in different while loops? What is the best way?

Thanks,

Nuno

[Christian Mergl]

Well,

The main thing to consider is that you are limited to 3 DMA channels.

The best practise should be to collect all your data you want to send in a parallel loop and use one DMA Target to Host FIFO to write it to the Host.

Christian