05-18-2010 02:53 PM
So I am using the FPGA NI-987x serial port loopback example code to write and read to ports on my 9871 module. I am using sbRIO instead of cRIO but that shouldnt matter.
I am writing to the port and then reading back from that port. My code requires that I write/read to one port, followed by a write/read to a second port, then a second write/read back to the first port.
Right now I am getting a time out on the second port and that affects the second write/read back to the first port. If I diagram disable thewrite/read to the second port and just do my two write/reads to the first port it works fine.
Something about the second port timing out causes the second write/read back to the first port to not write the first byte. All remaining bytes are written.
I have looked at the code and can't see anything that would cause the first byte to be missed. Is there some module reset that must happen after a single port times out?
05-19-2010 11:41 PM
Greetings Doug,
I am sorry to hear that you are having problems. I was wondering if you might be able to post your code so I can take a look at it. I do not know of any module reset that might happen after a signal port times out, but I will look into it further
At first glance, I wonder if by placing each of your ports in parallel and using a flat sequence structure might be a better way to go about it.
I look forward to see code.
05-20-2010 08:49 AM
Here is my code. I don't mind placing in parallel. But I'd like to find why to identify what in the code that could cause the first byte to be missed????