fpga compilation extremly slow

[Paljano]

Hey guys,

Im hoping Im right here. My problem is that when I try to compile my fpga VI, Xilinx 14.4 needs more than 9 hours to compile.

One example is that the program needs for this:

"INFO: [Designutils 20-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncIReset/c1ResetFromClk2.  Adding 1 LUTs and 3 Flops to estimation."

a few minutes. I think there are thousends of that messages in the log. Why do the compilation need so much time?

My System:

Intel Core i5-3337U CPU @1,8 Ghz

4GB Ram

I have a SSD with round about 30 GB left. I think you need more informations. Please tell me what else do you must know that you can help me.

Thank you

[Sam_Sharp]

When your FPGA compilation completes, what % of resources does it use on the FPGA (i.e. are you close to filling it)? What device are you compiling for? How complex is your FPGA VI and what sort of functionality does it perform? (FIFOs, complex math?)

I know there are certain conditions that can make routing the FPGA very difficult for the compiler (trying to route lots of signals to physical pins that are far apart) or you might be using operations that make the code very inefficient (such as doing lots of divisions, handling arrays or floating point arithmetic).

I don't expect it to make a lot of difference, but on your FPGA build specification settings (Xilinx Options) are you optimising for compilation speed or resources?

As is normally the case - if you could post your VI it may help to identify the cause of the issue. The error seems to be related to a shift register but without seeing what you're trying to do with it it's difficult to assist.

[Aditya_Dhananjay]

Hi Sam,

Your reply is very useful. However, if I may ask a few follow-up questions:

Is it possible to know a-priori how many division blocks I can use safely (no blow-up of compilation time or resources)? Similarly, how big can my arrays be before the compilation slows down, or the FPGA runs out of resources? Are there any rules of thumb?

Waiting around 6-9 hours for each compilation makes the task impossible to diagnose otherwise.

Finally, besides arraysor division operations, is there a list of other things to avoid?

Thanks!

Aditya

[Paljano]

Hello,

Im sorry for letting wait you with my answer. I solved my problems and have forgotten this thread.

So what you have to know is that you cant compile your projekt with windows 8. I installed the compiler on a windows 7 pc and use it to compile the projekt over network and this works fine.

You should not use so big arrays. Write your source code without building big arrays. When you need the data you can send it to the real time module. My compilation crashs with arrays with a size of about 100 till 200 elements. When you use many things on the frontpanel it will consume much ressources too.

[Sam_Sharp]

No problem - there's also another great tip I found out about recently which can improve FPGA compile times by up to 40% (on certain Intel CPUs - ones that have the Turbo Boost feature).

http://forums.ni.com/t5/LabVIEW-FPGA-Idea-Exchange/Multi-core-Compiling/idc-p/2301338#M297

[Paljano]

Oh, thats really nice to know. I will try it in the next days.

Thanks