fpga clip external clock

[nickstorton]

Hi All,

I have some IP which I have been given and I have created a CLIP interface in my project and that all appears OK. The IP has 3 clock inputs defined which seemed to be OK when I created the CLIP interface but now I need to route real world clock signals through the FAM and into both the CLIP and the LV FPGA code I am writing. The only thing is I cannot see any way of routing the external clocks to the CLIP. Has anyone done this before who can give me some help.

Thanks,

Nick

[Jamie_J]

Hi Nick and thank you for the query.

Firstly, can I clarify what hardware you are using as CLIP support can be hardware specific? 

Secondly, are you are familiar with the fundamentals of adding Socketed CLIP to an FPGA Target? Forgive me if you have already seen the below document however I believe it is a useful point of reference initially for this process:

Importing External IP Into LabVIEW FPGA - http://www.ni.com/white-paper/7444/en

Is this the stage you have currently reached with your application?

Regards

[nickstorton]

Hi Jamie,

Thanks for the reply. I'm using a PXI-7953R FlexRIO with a 6581 DIO FAM. I have been able to add the CLIP to my project but the problem I have is, if I declare the appropriate signals as IP clocks during the import phase I cannot then get access to them from the LV FPGA code I'm writing as the interface between the CLIP code, the IO hardware and the Windows host. The issue is that if I declare the clock inputs to the CLIP I cannot find any IO nodes that will allow me to connect an externally derived clock through the FAM and into the CLIP code.

Thanks,

Nick

[nickstorton]

OK so I've been looking into this a bit more and have managed to get my two external clocks into the HW and on into the CLIP by using the two IO Module Clock inputs. Whilst this might work with this particular project I can see future projects requiring more than just two external clocks which is why I wanted to be able to use any of the IO module input ports. Is it possible to define any HW input port as a clock input and then use that throughout the LV FPGA design, including CLIP?

Thanks,

Nick

[Dave.T]

Hey Nick, 

Our newer modules have the clock in the CLIP as FPGA IO instead of brining it in through IO Module Clock.  You should be able to compare the difference in the NI 5781 CLIP (IO Mod Clock) against the NI 5782 (FPGA IO) and see how we do it. 

You can find the VHDL and XML files in this folder:  C:\Program Files (x86)\National Instruments\Shared\FlexRIO\IO Modules

If you don't have those files, you can Download it here

[drummaniac83]

Nick,

Which RIO card are you using?  I would like to use an external clock with a SCTL on a 7852R, but most forum posts seem to indicate it is only supported on FlexRIO.

I spoke with a digital design engineer and he said he used VHDL code in an IP node to access an external clock on a 7852R, so i'm not sure if the limitation is a hardware one or a software one.

Thanks,

Josh

[nickstorton]

Hi Josh,

I'm using a PXI-7953R FlexRIO with a 6581 DIO FAM.

Nick

[vinodh_cyp]

Hello

My (simplified) application is to test two independent SPI masters in the DUT in parallel. For this purpose I want to emulate two independent SPI slaves in the FPGA. Each of the SPI slaves should be clocked by the corresponding master in the DUT. This means that the clock for the SPI slave has to be provided externally from the DUT. For this purpose I want to use two DIO pins as clocks for the slaves. Is this possible?

I am using PXIe-7966 with NI 6581.

- Vinodh

[nickstorton]

Hi Vinodh,

Take a look at the NI SPI IP available through the JKI VI Package Manager. This allows multiple Masters and/or slaves to be instantiated into your FPGA. So far I've got up to 16 independent slaves working on my FPGA.

Best Regards,

Nick