fir filter timing performance

[rftech]

Hello,

I'm working on a N210 USRP and I fetch RX IQ complex (CDB) data by packet of  20k samples. The IQ rate is 1MS.

Next I do a classic psd to detect a specified carrier, recenter the signal in the baseband and transmit the IQ samples to a FIR Filter (NI FIR Filter of the NIAALBase.lib FIR Filter vi). My problem is I obtain a RX buff overflow error since my treatments are too long.

I launched the profile performance and memory tool thinking that I had a memory problem. The profile memory and performance tool revealed that it was my fir filter which consumed too much time. The filter is aLPF whose coeff have been calculated througth the Matlab tool. 512 coeff are applied and I am in a continous config.

I don't understand why it takes so long to do the filtering. It'a a basic operation. I would like to avoid to decrease the IQ rate of the system and I would like to work on 20k data. Is there an alternative solution to my problem not to touch to these parameters?

Thanks for your response.

rftech

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[pbelles]

Hello,

Do you use the FPGA onboard of your USRP to do the filtering (according to the Ettus datasheet : https://www.ettus.com/content/files/07495_Ettus_N200-210_DS_Flyer_HR_1.pdf, there is Spartan 3A-DSP 3400 FPGA onboard your USRP)? This FPGA has 126 DSP48 (http://www.xilinx.com/support/documentation/data_sheets/ds610.pdf), which are particularly useful to optimise the +/x operations made for filtering.

If you don't use the FPGA onboard, then the computations are necessarily done on the CPU of the host PC. The performance of the computation are then limited by the characteristics of your PC.

Do you have the labVIEW FPGA module? If you do, then you can program the FPGA of your device (https://www.ettus.com/downloads). Also, with the labVIEW FPGA module comes the Xilinx IP functions (http://zone.ni.com/reference/en-XX/help/371599L-01/lvfpga/fpga_xilinx_coregen_pal/). Among them (http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgahelp/fpga_xilinxip_descriptions/), you have the FIR Compiler. This compiler (made by Xilinx) aims at optimising the speed of FIR algorithms on FPGAs (using DSPs and various algorithm optimation techniques). You might want to use it if you have a speed problem.

Finally, I can suggest to you to follow the training "High Throughput" which tackles all the issues related to code speed and throughput.