dma transfer between host & target

[muks]

Can you also give a breif description?

[Alann]

Oh I was typing my query in a notepad & forgot to paste it. Sorry!

So here i am trying to pass two data streams from host to target FPGA through FIFOs. I want to process these data streams on FPGA & write the output in another FIFO & give it back to the host. I have made a simple model for it. Forgive my ignorance but i dont understand the behaviour of the program when i set Count ( Loop Timer) to a low value like 20 ticks. What is actually happening when i want the FPGA VI loop to run faster? What I can i do to make sure that no output data is lost? Secondly are there any other constraints while using multiple FIFOs?

I am using PXI-7842R & LabVIEW 8.6.1

Regards,

[muks]

Will this be of any help?

[Alann]

No!

Message Edited by Alann on 10-09-2009 02:25 AM

[muks]

have u seen this?

[Anna_K.]

Hello,

Have you seen the Host synchronization examples for cRIO? You could implement triggers to ensure that the host and FPGA FIFOs are timed properly.

THanks,