I've been having some trouble using a host to target DMA FIFO on a Compact RIO- I don't have much experience with this so please bear with me! I haven't been able to find the answer to this in any of the resources online or any of the community posts so I hope this isn't a repost.
What I want to do is pass an array of 3 elements through from the RT host side to the FPGA target. I've done this in reverse, from target to host, but it doesn't seem to work now I'm trying it from host to target. The method I used to do this before was by creating an array of data in a fast running loop for acquiring the data, then passing this array using a local variable to a seperate loop, also running on the FPGA, that uses an indexing for loop to write the elements one at a time into the FIFO. This seperate loop is set to run at a slower rate so that the RT side can keep up and I don't get overflow of the buffer, and I always know which element in the array is which when the array is unpackaged on the RT side.
I'm trying to implement the same method in reverse, creating an array on the host side and using an indexing loop to write to the FIFO. The problem I have is that it seems that the FIFO write method on the host side actually seems to need an array passed to it, rather than a single element. If I write the array as it is on the host side, the read block on the FPGA side expects a single element out. I'm not sure if this is because it will automatically pass data out one element at a time, but if I put it in a for loop so that I can build an array so that I can see the data coming through, I have no indexing input to the for loop... I couldn't see how I could use the 'get number of elements' method to do this.
Hopefully from this you can see what I'm trying to achieve- I would be very grateful for any advice any of you could give me as to what I'm doing wrong or how I could do this better!
Thanks in advance
Would it be possible to post your code on to this thread so that we can take a look at what you have done so far?