crio 9063,ni 9467 and ni9234 time sync using gps(pps)

[timer22]

Hello.

I would like to acquire data using Ni 9467 (gps module) and Ni 9234 (51.2 kHz sound and vibration daq module) using CRIO-based fpga.

Currently implemented fpga-vi uses FIFO to combine PPS TIME STAMP with analog input values.

In fact, the same signals are distributed and stored in two sets of systems, resulting in different TIME STAMP values.

I don't know where the problem is.

Exactly what I want to implement is to replace wired connections by giving them absolute time using GPS to measure signals in two distant systems.
Give me a tip.

A time stamp value of 51.2 kHz is required.

[Jimmie_A.]

Hi,

What you want is possible, will require some work though! If I understood things correctly you would like to achieve multi-cRIO chassis synchronization, correct?

Fairly common request, and the challenge is to achieve proper alignment (start at the same time) and clock disciplining (each cRIO use their own timebase and DSA modules user their own oversample clock all resulting in clock drift over time), FPGA timekeeper combined with the time-based synchronization provided by the NI-9467 and resampling (needed since DSA modules user their own oversample clock and the timekeeper cannot compensate for it, so you need ARC resampling) would provide the best results.

FPGA Timekeeper implements a PLL on the FPGA to discipline a counter over a reference signal and that reference signal could be your PPS from the 9467.

https://forums.ni.com/t5/Sync-Labs/NI-TimeSync-FPGA-Timekeeper-Getting-Started/gpm-p/3543895

Hope this helps! 

[timer22]

Thank you for your help.

I tried a timekeeper, but there was an 1ms error in the results of the two CRIO system.

Each CRIO has the same configuration and operates with the same code.
It was just a different laptop for control.

 AI,GPS(PPS)  Acquisition = FPGA

post-processing = Window os

(Realtime is not used.)

here is code Snapshot, What should I do?

* ni 9467 (100ns, Resolution)

i don't understand 8ms error.....

#1 and #2 .. code;

#3 .... result (0.6~0.8ms error)

test -  source distributed to each CRIO with each gps

[AlejandroZepeda]

Hello, timer22.

Make sure that you also have somewhere in your diagram Timekeeper.vi outside of any loops or sequence structures (I don't see it in your screenshots).

Also, what is the sampling frequency for your AI acquisition?

I ask because I wonder if what is happening in the diagram depicted in timeke1-1.jpg is that in the upper right while loop the timekeeper time is read much earlier than the actual analog sample is taken. Perhaps you would need to have a sequence structure in that loop reading the analog channels in the first frame and the time in the second frame, to ensure that the reading of the time occurs as close as possible to the sampling.

Hope this helps.

Regards,

Alejandro

[timer22]

thank you for ur comment

firest. timekeeper.vi put the outside loop

second. AI  sampling frequency 51.2kHz

just now. i will try sequence structure code ,as you say

Thank you very much for your interest.
Thank you as a beginner in fpga and labview.

If use the sequence structure, 1 hz data input at first sequence and  PPS signal input at second sequence, this pps signal is 1Hz???

And set to extract 5120 elements from fifo.

If I use sequence structure, if I take out 5,120 data, (0.1 seconds, AI signal), timekeeper gets 5,120 data divided by ns.
So, should I use a loop timer to divide the PPS into 51,200 pieces per second?

[AlejandroZepeda]

Hi.

The bottom while loop does indeed run at 1 Hz. This is enforced mainly by the Wait for PPS node.

The top while loop should continue running at 51.2 kHz. In that loop all you'll have is a sequence structure with the analog sampling in the first frame and Get Time.vi in the second frame.

By the way, another thing to check: what is your top-level clock frequency? The timeout values in the bottom loop assume your top-level frequency is 40 MHz.If it is a different frequency, then the timeout values must be adjusted (ie. if your top-level frequency is 80 MHz, then the timeout for the Wait for PPS node should be 82M and so on).

Regards,

Alejandro

[timer22]

YES. 40Mhz clock....

When using sequence structure  and fifo

IF.... 

array time : Fpga Timekeeper time(100Hz)  =  0 ,  0.01 , 0.02 , 0.03 , 0.04 , 0.05 , 0.06 , 0.07 , 0.08, 0.09 , 0.10 ~~~~ 1

array Ai     :                                     (10 Hz)   =  0  , 0.1 , 0.2 , 0.3 , 0.4 , 0.5 , 0.6 , 0.7 , 0.8 , 0.9 , 1

if i get the data sampling frequence 10Hz and build array using fifo,

1 sec result is

get array time : Fpga Timekeeper time(100Hz)  =  0 ,  0.01 , 0.02 , 0.03 , 0.04 , 0.05 , 0.06 , 0.07 , 0.08, 0.09 , 0.10

get array Ai     :                                     (10 Hz)   =  0  ,   0.1 ,   0.2 ,   0.3 ,   0.4   , 0.5 ,   0.6 ,   0.7 ,   0.8 ,  0.9 ,      1

2 sec result is

get array time : Fpga Timekeeper time(100Hz)  =  1 ,  1.01 ,1.02 , 1.03 , 1.04 , 1.05 , 1.06 , 1.07 , 1.08, 1.09 , 1.10

get array Ai     :                                     (10 Hz)   =  1 ,  1.1 ,  1.2 ,   1.3 ,   1.4   , 1.5 ,   1.6 ,   1.7 ,   1.8 ,  1.9 ,   2

I think this problem is based on the number of elements in the sequence structure and the FIFO at the same time.

How shall I do it?

I want to get an array of matching two groups.

And if I do as attached, if I call the FIFO set at 5120 elements, will there be TIME matching each AI element?

[timer22]

I think I was wrong.

fpga clock is 40Mhz --> 1 / 40000000 = 2.5e-8

AI sampling is 51.2 kHz --> 1/51200   = 1.9531e-5

and fpga 1 tick is 2.5e-8 [s]

1.9531e-5 / 1 [tick] = 781.24

and i want loop timer set that's number (781.24 tick)

How do i handle decimal points? (0.24 tick)

1tick * 0.24tick = 6ns

it's means 1 loop time error is 6ns????

1[sec] later 0.3072[ms] error...

what is the best?? i set loop counter 781 or 782??

[AlejandroZepeda]

Hello.

I am actually not very familiar with the NI 9234 module you are using, but from what I can see in the datasheet, it has a fixed sampling frequency at 51.2 kS/s per channel.

Since your diagram runs at 40 MHz, you are right, there is no integer divisor between the 2 periods (25 ns and 19,531.25 ns).

So, the best thing you can do is get a timestamp as close as possible to the actual sample time.

So, for example, if your initial sample was timestamped at, say, time 3,609,500 ns, I would expect the following timestamps:

Sample	Timestamp (ns)	Difference
1	3,609,500
2	3,629,032	19,532
3	3,648,563	19,531
4	3,668,094	19,531
5	3,687,625	19,531
6	3,707,157	19,532
7	3,726,688	19,531
8	3,746,219	19,531
9	3,765,750	19,531
10	3,785,282	19,532
11	3,804,813	19,531
12	3,824,344	19,531
13	3,843,875	19,531
14	3,863,407	19,532
15	3,882,938	19,531

Notice that the difference between the timestamps is 19,531 ns 75% of the time and 19,532 25% of the time, reflective of the 0.25 inaccuracy between the 2 frequencies.

I am assuming that the node where you read the AI data blocks until there is a new sample for each of the channels, thus making the upper loop run at 51.2 kHz automatically.

If this is the case, you should not need to add the wait like you have in timeke4.png.

But the frames should be inverted. You should read the AI data first and get the timestamp afterwards, and put the timestamp in the same array as the samples, like you had in timeke1-3.png.

I know these descriptions can be a bit difficult to follow. I wish I could send you a screenshot of what I mean, but I don't have LabVIEW FPGA available here at the moment.

Good luck.

Alejandro

[timer22]

Thank you. Your advice helped me a lot.

I have two items now.
GPS and AI.
The PPS signal collected from the GPS signal is 1.0e20 units.
And it's about 1.0E-7 for AI.
If I mix these two items into one array, the PPS is the standard.
The number 9.23824891E20 (PPS) and 0 (AI) are returned.
So putting it in the same array is an error.
How can I put GPS and AI into each FIFO and have an accurate return?

And I realized.
There is no error in the 5.12 MHz clock setup in the FPGA.
51.2 kHZ and 5.12 MHz are only 100 times the difference.
What do you think about using TIMED LOOP using this?