convert the speed of the while loop on MyRio 1900 from the millisecond range to the microsecond range

[ashrafayasrah]

Thank you @rolfk
I will try to go through "fixed point floating-point arithmetic" to see if I can use it or not.
i will attach my vi. and the algorithm code.

[ashrafayasrah]

Thank you for helping me @altenbach

First of all, I have designed a new circuit [please see the attached] for a battery energy storage system which requires a cell state of charge (SoC) balancing strategy. I have designed a suitable algorithm and test it successfully by the Matlab.

The algorithm seeks to control the switches states of the circuit during each level of a multilevel output voltage to generate a multilevel output voltage and achieve SoC balancing among all the cells (batteries). I have attached the vi. file and the .m file (the algorithm code). The algorithm attaches is just a draft.
As the input for the algorithm, I need to read the cells' voltages, the circuit current, etc, then by the algorithm, I will decide each switch status as ON or OFF during each time step.

By the way, this work has been done by MATLAB Simulink, so I need to validate it by hardware.

i have used some of the Matlab functions to write the algorithm as code (such as sort, min, floor, abs,...), that is why I feel it will be difficult to convert it to the graphical code also the graphical code maybe will be bulky.
Briefly, for the real electrical system, we use 50 Hz which means that I have 50 duty cycles per second. To generate 80 volt, for example, I need to divide each duty cycle to 64 part (time step), thus, 64x50=3200 steps per second. That is why I need high speeds. Hope you can help me to insert the algorithm code in the LabVIEW FPGA.

[ashrafayasrah]

Thank you very much @T-REX$

Hope this idea can address my problem. I will go through it to see how to bring the code to LabVIEW FPGA. I will update you.

[rolfk]

Looking at your MathScript file, I do not see anything complicated at all. That would fit easily in one or two subVIs inside a loop on the FPGA and take most likely a lot less time to develop than trying to get the Mathscript=>HDL=>LabVIEW IPN workflow fully working.

Not that the resulting HDL code should be complicated or large (if the MathWorks HDL generator is worth anything) but as T-Rex said it's not an often walked workflow path, so expect to find some bears along your way that you will have to slay yourself. Also the LabVIEW IPN has a few limitations in what flavor of VHDL it will accept and if MathWorks generated VHDL does use any of those features it's going to be extra painful to have to manually edit the VHDL files every time to make them workable for the LabVIEW IPN.