LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

compile error internally pipelined

I need to generate a PWM signal based on a sine wave input using a PXI-7831R and LabView FPGA 2009 SP1. It appears that the Triangle Wave Generated PWM may be a good starting point. http://decibel.ni.com/content/docs/DOC-2387 I have placed the sample code for the example cited above in a project for the PXI-7831R. A compiler error is generated. Internally pipelined object(s) not connected to a feedback node. The error points to the "Look-Up Table 1D 'Triangle Wave 1D LUT'". The output of the LUT has a feedback node. Has the compiler changed since LabView 8.6 such this is now an error condition? I have tried some fixes, but none have corrected the error. What is purpose of the initial value of 275 on the feedback node for the index count into the Triangle Wave table?

 

 

0 Kudos
Message 1 of 5
(2,018 Views)

wantacobra,

 

I was able to compile Clock Deriver.vi and TriangleWavePWMGen.vi in both LabVIEW 2009 SP1 and 2010. I think the trouble is that the TriangleWavePWMGen test.vi is meant to run in the Windows and not in FPGA. It is just a tester to prove that the TriangleWavePWMGen.vi works.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Ben Sisney
FlexRIO V&V Engineer
National Instruments
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 Kudos
Message 2 of 5
(1,990 Views)

Ben

 

Did you compile the test VI with the SCTL to run on the host and not the FPGA?  What is the implication of running code in a SCTL on the host?  Ben_B developed this code.  Is he available for questions?

 

Mike

0 Kudos
Message 3 of 5
(1,971 Views)

wantacobra,

 

I did not compile the test VI as it is not compilable (you can't have a FPGA sine wave generation in a SCTL). Running a SCTL on the host PC is not possible as the SCTL just becomes a normal Timed Loop. I personally do not know Ben_B, but posting on the example as you did is a great way to try and ask questions about his example.

 

Again, though I'm not 100% sure, I'm pretty sure the Test VI was meant to run on the Host side to call the other 2 VIs (on the host, not FPGA yet) to simulate what the fpga code will do. You then move the other two VIs to the FPGA and compile them.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Ben Sisney
FlexRIO V&V Engineer
National Instruments
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0 Kudos
Message 4 of 5
(1,959 Views)

Alright.  I've updated the text in the posting to make the comments that echo Ben's thoughts, and I've added a really simple example that will compile to FPGA.

 

I hope that helps.

 

~Ben

0 Kudos
Message 5 of 5
(1,939 Views)