I have a basic question about the relation between the clock rate and ADC sampling rate. We have bought a NI 5761 which on the manual it said the external clock is in the range of 175-250MHz, but in the example of the "Low speed clock selection", It is claiming that the sampling rate is 150MHz. Will this be a problem. If I give an external clock at 80MHz (the maximum clock rate from our data generator), will this board working for sampling at 80MSPS?
And another question is one of my project code was using the "single sample clip" which is runing at high speed. There were 2 single cycle time loop included, I give each of them a clock source "IO Module Clock 0" for the data to FIFO, and a clock source "IO Module Clock 1" for the FIFO data processing. I have tried to change the clock 0 from 80MHz, 100MHz, and 250MHz. It always give me a time loop time violation error (For the "data to FIFO" part it is 4ns missed 0.42ns and for FIFO data processing part it is 8ns missed 0.32ns). This clearly shows that eventhough I have changed the clock rate of the clock source on different single cycled loop, the code actually does not change, they are still trying to compile at 250MHz for clock 0 and 125MHz for clock1. So how could I change the clock rate for single cycled loop containing the "single sample clip" method nodes?
Another question is if I run it at 75MHz, and the single cycled loop is still 150MHz, will one sample being rewrited twice to the on board FIFO or just one?
I believe you should be able to use your 80 MHz external clock with the Low Speed Clip. The example in the example finder actually has IO Module Clock 0 set to 50 MHz by default. Check out the example under Hardware Input and Output >> FlexRIO >> IO Modules >> NI 5761 >> NI 5761 - Low Speed Clock Select.lvproj.
You can also find some good documentation on this clip in the help menu found here. Once you open the help file, navigate to NI FlexRIO Adapter Module Support >> Configuring Your Adapter Module... >> Configuring an NI FlexRIO Adapter... >> NI Flex RIO High-Speed Digitizers Adapter Module >> NI 5761 Component-Level IP... >> NI 5761 Low Speed CLIP.
Thank you for yor reply!
I have checked the manual of NI 7951R again. It says that the IO module clock 0 is directly connected to the sampling clock, which means that eventhough I have changed the IO module clock 0 (lets say it is 50MHz) it will stick with the current sampling rate, is this correct?
Many thanks for your reply!
According to your explaination, if I use the "single sample clip" which is runing at 250MHz internal clock rate, no matter what I set to the I/O module clock 0, it always try to compile at 250MHz right?
And if I use the low speed clock selection clip, it will run according to my external clock rate, in this case, I can set a range or certain rate (such as 80MHz or 50MHz to 90MHz). After I compile the vi, it will only allow me to run at this range of clock rate?
If you want to use an external clock with the Single Sample CLIP, you have to specify this with the Sample Clock Select input. Look at the attached screen shot. This shows where you can find the input in your project explorer, and it also shows a portion of the help file that explains your different options for the Low Speed CLIP.
With the Low Speed CLIP, the external clock is the default setting. As James said, you still have to tell the computer what frequency of clock to expect so that LabVIEW knows how to compile the VI. This is done by changing the frequency of IO Module Clock 0.