Showing results for 
Search instead for 
Did you mean: 

can i implement RS422 protocol using 7831 RIO card

please tell if i can implement RS422 protocol using NI FPGA card. Also please help me on how to do the same...
0 Kudos
Message 1 of 4
You can definitely implement the RS-422 protocol on the FPGA card. Check out the RS-232 on FPGA example on DevZone. RS-422 may be a bit different than RS-232, but not very much. The main thing you will have to deal with are the voltage levels of the signal. The FPGA DIO are single-ended 3.3V TTL, while RS-422 is a differential voltage signal. So to have a true RS-422 interface you will need to add a signal translator between the FPGA card and your RS-422 device(s).

Christian L
authored by
Christian L, CLA
Applications Engineering Senior Manager - Automotive and Transportation
NI - Austin, TX

Message 2 of 4

I am trying to implement RS422 using the FPGA on a NI cRIO 9401.  I modified the FPGA Serial Example mentioned in this post.  Using a custom PCB board designed in house we take the TTL serial output and input from the cRIO module and translated into differential 5V RS422.

If I loop back the transmit and receive on the PCB board I can send and receive a text message ok.

But when I try to connect the PCB board to PCI-422 card by connecting the transmit positive to the receive positive and transmit minus to the receive minus, the text I read back is incorrect and sometimes looks like nonprintable characters. I checked the pulses that both ends generate with an oscilloscope and they look similar. 

Do you have any suggestions? 



Director of Engineering
G Systems,
Certified LabVIEW Architect
Certified LabVIEW Embedded Systems Developer
Certified Professional Instructor
0 Kudos
Message 3 of 4
Hey Russell,

One thing you could try to verify that you are encoding the characters correctly would be to write a series of characters from the PCI-422 to an oscilloscope, and then to write the same sequence from your 9401. This way, you could check that they are the same and that you have not made a mistake on both the transmit and receive end of the FPGA.

Best regards,
0 Kudos
Message 4 of 4