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calculate the delay caused by the vi

Hello everyone

 

I have created a vi to generate 1PPS from the current time of the computer and transmit it to an Time Interval Counter (TIC) using a DAQ card. I need to calculate the delay occured in the whole processing of the vi, including generation of 1PPS signal, loop and DAQ card delay. How can I calculate this delay. Kindly help me.

 

I have attached the vi for generating 1PPS signal.

 

Thanks

rchkrishna

 

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Message 1 of 11
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If you are just looking for the loop iteration time, use a Feedback Node to record the "previous" iteration's time and subtract from the current time.


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I envy everyone who can understand the concept of the feedback node.  It seems I have a mental block about it; as hard as I try to understand it, my brains just says, "Nope, not gonna happen," and just shuts down.

Bill
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Proud to say that I've progressed beyond knowing just enough to be dangerous. I now know enough to know that I have no clue about anything at all.
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Relying on (Windows) software timing for hardware signals is in most cases not accurate. Why don't you simply create a 1 Hz signal hardware timed?

 

Norbert

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You can think of the feedback node as an in-place shift register, as in, a shift register where you don't have to wire all the way to the outer edge of the loop.

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@billko wrote:

I envy everyone who can understand the concept of the feedback node.  It seems I have a mental block about it; as hard as I try to understand it, my brains just says, "Nope, not gonna happen," and just shuts down.


A feedback node is literally exactly the same thing as a shift register.  The only difference is that the feedback node does not have to be bound to a loop.  Being a CLD, I sure hope you understand shift registers.


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@crossrulz wrote:

@billko wrote:

...


A feedback node is literally exactly the same thing as a shift register.  ...


Until you get to that initializer terminal and the difference between running in FPGA...

 

But can certainly not claim to know embeded as you do. (smiley-tips-hat)

 

Ben

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@rchkrishna wrote:

How can I calculate this delay. Kindly help me.

 


Unfortunately, you cannot "calculate" that delay, because it depends on an infinite number of hardware and software parameters and will be different on every single computer. You actually need to measure it!

 

Tims's code is OK for measuring the loop time, the only thing I would do is wire the time also the the global feedback initializer. This way you get zero instead of a random very large number in the first iteration.

 

Some additional comments:

  • I imagine you know that your case structure makes no difference and could be deleted without any change in functionality.
  • There is absolutely no need for any dynamic data here. What new insights do you expect by converting a scalar boolean to dynnamic data then to a DBL (???) and a boolean array? Makes no sense!
  • You are hammering the DAQ assistant as fast as the computer allows with boolean data even if the data did not change from the last call. You only need to write if the value is different.
  • How long should the TRUE "pulse" be? Currently it is a random function of hardware. You might even accidentally skip pulses if the loop delay is longer than expected (e.g. during a windows update and such).
  • What you need to do instead is use a timed loop and generate a "TRUE then FALSE" signal whenever a pulse should occur. You probably could even use hardware timing if your hardware allows.
  • If you need better precision, you need to go to LabVIEW RT or even FPGA. Windows is not suitable.

 


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@crossrulz wrote:

@billko wrote:

I envy everyone who can understand the concept of the feedback node.  It seems I have a mental block about it; as hard as I try to understand it, my brains just says, "Nope, not gonna happen," and just shuts down.


A feedback node is literally exactly the same thing as a shift register.  The only difference is that the feedback node does not have to be bound to a loop.  Being a CLD, I sure hope you understand shift registers.


LOL actually I just figured it out.  If you apply the rules of dataflow, it can only behave in a very predictable manner.  Mystery solved for me.  I have no idea why it took me so long to figure it out.  Like I said, mental block.

Bill
CLD
(Mid-Level minion.)
My support system ensures that I don't look totally incompetent.
Proud to say that I've progressed beyond knowing just enough to be dangerous. I now know enough to know that I have no clue about anything at all.
Humble author of the CLAD Nugget.
Message 9 of 11
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@crossrulz wrote:

@billko wrote:

I envy everyone who can understand the concept of the feedback node.  It seems I have a mental block about it; as hard as I try to understand it, my brains just says, "Nope, not gonna happen," and just shuts down.


A feedback node is literally exactly the same thing as a shift register.  The only difference is that the feedback node does not have to be bound to a loop.  Being a CLD, I sure hope you understand shift registers.


Also, I thank you for your vote of confidence after all these years on the forum.  I see I've made quite an impression on you.  So I will just hang out in the background while you field all the "tough" questions.

Bill
CLD
(Mid-Level minion.)
My support system ensures that I don't look totally incompetent.
Proud to say that I've progressed beyond knowing just enough to be dangerous. I now know enough to know that I have no clue about anything at all.
Humble author of the CLAD Nugget.
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