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cRIO 9068 FPGA high device utilization

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Hello. I'm having problems with my cRIO 9068 (667MHz dual-core, Artix 7) which is using a lot of FPGA resources. I made a small FPGA VI (LabVIEW 2013 SP1) which switches USER FPGA LED in both colors(green and orange) for 500ms and then it is switched off for another 500ms. Device utilization report shows 9193 registers used(8.6%) and 9744 LUTs (18.3%). I adapted the same VI for an cRIO 9072 (Spartan 3 - 1M) which I have available and device utilization is much lower: Registers used: 443(2.9%) and LUTs: 644(4.2%) - please see attachements!

I used the XNET libraries in the past with the 9068 and 9862 CAN Module: since I knew that these libraries are using FPGA space, I removed XNET 1.8 from cRIO software before this test. Before removing, FPGA utilization was even higher!

Can anyone tell me how can I reduce the used resources to "normal"? Thank you!


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Message 1 of 4
Accepted by topic author LucianM

Hi Lucian,


The increase in base resource utilization that you're seeing is normal for the Zync family of targets. Try compiling blank VI's for each (no user written LabVIEW code). You'll notice that the Zync patform still utilizes a substantial portion of the fabric (depending on which specific Zync target is used).


This behavior is due to the very different architecture of the Zync family of chips. Since the FPGA and ARM processors are on a shared die, much of the logic and processing NI implemented in ASICs on Spartan/Virtex boards had to be moved onto the FPGA itself.


You should also notice that, while there is an increase in base FPGA fabric usage, the raw number of LUTs/flops available to you as a user is still much higher on Zync targets than a comparable Spartan device.


Message 2 of 4

Thanks @T_REX$ for your quick reply!

So this additional code that had to be implemented in FPGA in Zync chips will remain constant or it is dependend on user FPGA code? In other words, the remaining available resources can be used entirely by the user or additional code might still be added in FPGA depending on user code complexity? I'm worried because the final code for the project I'm working for will be quite complex and might be hard to fit in our target.


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Message 3 of 4

Hi Lucian,


The resources utilized by NI should remain static, to the best of my knowledge.


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