buffered counter mode4 on PXI6040

[Andreas2]

I use a PXI 6040. The counter 0 is configured with external gate, external source, buffered mode 4 HIgh level gating.

The measurement is running. What I mean is, that some High-Phases have occured at the gate and during such High-Phases the source-line was pulsed externally. Therefore the buffer already has some values stored. The problem I see is the following:
the clock-source-line is low, now the gate-line is going to high. But now there are no pulses at the clock-source-line. Then the gate-line returns to low. This returning to low triggers a taking-over of the counted-value to the buffer. But what I read in the buffer is not a 0 (becaus no clocks have been present during High-Phase of the gate). I read the old value of the pe
riod before. This is bad because I can interprete this copy of the old value as a currently measured new High-Phase.

Is this problem known and is there a solution in that way, that the counter would deliver a 0 to the buffer for the case that no clock-source-pulses will ocure during high-level at the gate ?

[Spencer S.]

Andreas,

What you are seeing is expected behavior, which can not be modified for the DAQ-STC, the counter chip used on the PXI-6040E. The NI-TIO, the counter chip used on the NI 660x devices, has a Synchronous Counting Mode that modifies this behavior. It is detailed in the following KnowledgeBase:

Common Questions Regarding the Synchronous Counting Mode for NI-TIO Based Devices (NI 660x, 455x, et...

Below, I have included a link to the product page for the NI 660x devices:

NI 660x Product Page

Good luck with your application.

Spencer S.