assign a Ext clock to SbRIO Clip

[mtzhang]

Hi,all

    I'm creating a SbRIO CLIP for NI-SbRIO-9607 by clipgenerator tool, and configuer DIO26 as a external clock to LV FPGA. Now in the test Vi ,I can select the DIO26 as a clock source for my SCTL, but when I complied the  vi, the FPGA Complie worker reports the following error :

Details:
ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets n_0_window/theCLIPs/RMC_Socket_CLIP0/IOBUF_26] >

then I add this rule to the xdc file, but it still not works, so what can i do now?

[mtzhang]

Hi,all

      使用SbRIO_9607的ClipGenerator生成了一个自己的Clip组件，其中包括一个外部时钟输入信号Clk_Ext，配置为内部预留BUFG，然后在测试程序中使用该时钟作为SCTL的时钟进行编译，出现以下错误：

Details:
ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets n_0_window/theCLIPs/RMC_Socket_CLIP0/IOBUF_26] >

按照其建议，已经在相应的xdc文件中增加了该约束，但是重新编译仍然出现该错误，不知道问题在哪里？麻烦高手指导下，谢谢了

[mtzhang]

Hi,all

      我在使用SbRIO_9607的ClipGenerator生成了一个自己的Clip组件，其中包括一个外部时钟输入信号Clk_Ext，然后在测试程序中使用该时钟作为SCTL的时钟进行编译，出现以下错误：

Details:
ERROR: [Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets n_0_window/theCLIPs/RMC_Socket_CLIP0/IOBUF_26] >

按照其建议，已经在相应的xdc文件中增加了该约束，但是重新编译仍然出现该错误，不知道问题在哪里？麻烦高手指导下，谢谢了

[RavensFan]

Don't create new messages with the same question.  The message has been merged into the other two so people don't waste their time answering different message threads.

[Spex]

DIO_26 is not considered 'clock capable' by Xilinx, because it does not have dedicated routing resources between the DIO pin and the FPGA clock distribution circuitry.  

Please see the sbRIO-9651 specifications (pages 18 and 29 to see clock capable documentation and available pins): http://www.ni.com/pdf/manuals/376962b.pdf

A quick Google search of your error message also pointed me to this Xilinx Answer Record: https://www.xilinx.com/support/answers/64452.html

Xilinx primary recommendation is to move the clock input to a clock capable pin, such as those listed on pages 29-32 in the sbRIO-9651 specifications (any pins with SRCC or MRCC suffixes). 

Xilinx strongly discourages attempting to use the override rule to demote the error to a warning, and NI can't confirm if your LabVIEW diagram will behave properly if a poor clock route is chosen between your external clock and the LabVIEW FPGA logic.  As to why the override rule isn't working, I'm not an expert in Xilinx .xdc constraints and format, but I would suspect that their may be a formatting error with the .xdc file ensuring that the rule is applied to the correct net.

[mtzhang]

yes, DIO26 is not the clock pin, but the general IO can be selected as a clock source in xillinx FPGA  in ISE when you  add the constraint "set_property CLOCK_DEDICATED_ROUTE FALSE" to this pin, as  the ClipGenerator suggest to do.I know that this will degrade the performance of the clock source,but it really will  work.

The clipgenerator also suggest to add the constraint to the DIO26, then this pin can be used as a clock input for the sbRIO, but i can't find the detail for the suggestion.so I add the 

< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets n_0_window/theCLIPs/RMC_Socket_CLIP0/IOBUF_26] > to DIO26 in the xdc file, but this does not works.

now my question is how to add the constraint to the DIO26 to make this pin a clock input for the SbRIO?

---

Spex 已写：

DIO_26 is not considered 'clock capable' by Xilinx, because it does not have dedicated routing resources between the DIO pin and the FPGA clock distribution circuitry.  

Please see the sbRIO-9651 specifications (pages 18 and 29 to see clock capable documentation and available pins): http://www.ni.com/pdf/manuals/376962b.pdf

A quick Google search of your error message also pointed me to this Xilinx Answer Record: https://www.xilinx.com/support/answers/64452.html

Xilinx primary recommendation is to move the clock input to a clock capable pin, such as those listed on pages 29-32 in the sbRIO-9651 specifications (any pins with SRCC or MRCC suffixes). 

Xilinx strongly discourages attempting to use the override rule to demote the error to a warning, and NI can't confirm if your LabVIEW diagram will behave properly if a poor clock route is chosen between your external clock and the LabVIEW FPGA logic.  As to why the override rule isn't working, I'm not an expert in Xilinx .xdc constraints and format, but I would suspect that their may be a formatting error with the .xdc file ensuring that the rule is applied to the correct net.

---

"

[tannerite]

Is there a specific reason DIO_26 must be used as a clock input in your application rather than a pin meant for clock inputs? Do you already have a PCB designed that routes an input clock to this DIO? If so, what is the frequency of this input clock? Spex above explains the specific reason why routing to a non-clock capable pin is not recommended, although the sbRIO CLIP Generator does not explicitly disallow it.

[mtzhang]

yes, DIO_26 was designed for the clock pin of the clip,and the LV FPGA complie Worker report the error as above, then  I chose a clock pin for the CLIP ,and it works now.

Now, I just want to know how to add the constraint  to the xdc file if a non-clock pin selected as a clock pin for the clip, thanks