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Xilinx FPGA compilations fails

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HI all,

 

I'm trying to compile a very simple FPGA code in the NI cloud compile service to run on a cRIO 9030; with only 1 module..
But I always get following error:

 

Below the log file:


****** Vivado v2013.4_(AR59519_AR59812_AR59814_AR60501) (64-bit)
**** SW Build 353583 on Mon Dec 9 17:26:26 MST 2013
**** IP Build 208076 on Mon Dec 2 12:38:17 MST 2013
** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: Implementation
WARNING: [Common 17-301] Failed to get a license: Implementation
WARNING: [Vivado 15-19] WARNING: No 'Implementation' license found. This message may be safely ignored if a Vivado WebPACK or device-locked license, common for board kits, will be used during implementation.

Attempting to get a license: Synthesis
Feature available: Synthesis
Loading parts and site information from /opt/apps/NIFPGA/programs/vivado2013_4/data/parts/arch.xml
Parsing RTL primitives file [/opt/apps/NIFPGA/programs/vivado2013_4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/opt/apps/NIFPGA/programs/vivado2013_4/data/parts/xilinx/rtl/prims/rtl_prims.xml]
# package require struct::list
# package require struct::set
# set_param synth.elaboration.rodinMoreOptions "rt::set_parameter reduceVariableBitSelect false; rt::set_parameter reinferPruneBitWidths false; rt::set_parameter constPropCarry false; rt::set_parameter maxRomAddrWidth 64; rt::set_parameter max_loop_limit 1000000"
# read_vhdl [glob *.\[vV\]\[hH\]\[dD\]]
# if {[llength [glob -nocomplain *.\[xX\]\[dD\]\[cC\]]] > 0} {
# set CoreXDCFilesFH [open CoreXDCList.txt r]
# set xdc_files_xci [split [read $CoreXDCFilesFH] "\n"]
# close $CoreXDCFilesFH
# set xdc_files_all [glob *.\[xX\]\[dD\]\[cC\]]
# set xdc_files_source [::struct::set difference $xdc_files_all $xdc_files_xci]
# set xdc_files [read_xdc $xdc_files_source]
# foreach xdc_file $xdc_files_xci {
# if {[file exists $xdc_file]} {
# lappend xdc_files [read_xdc -ref [file rootname $xdc_file] $xdc_file]
# }
# }
# set_property PROCESSING_ORDER {LATE} [get_files $xdc_files]
# }
# set_msg_config -id "Synth 8-3431" -suppress
# synth_design -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full"
Command: synth_design -top toplevel_gen -part xc7k70tfbg676-1 -flatten_hierarchy full

Starting synthesis...

Attempting to get a license for feature 'Synthesis' and/or device 'xc7k70t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k70t'
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 751.590 ; gain = 148.383
---------------------------------------------------------------------------------
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:295]
ERROR: [Synth 8-1031] knidmahighspeedsinksize is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:296]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:301]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:302]
INFO: [Synth 8-2810] unit pkgshimswitchedlinkdmaportifc ignored due to previous errors [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:68]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 802.402 ; gain = 199.195
---------------------------------------------------------------------------------
ERROR: [Common 17-39] 'source' failed due to earlier errors.
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 0 Warnings, 0 Critical Warnings and 4 Errors encountered.
synth_design failed
::ERROR: [Common 17-39] 'source' failed due to earlier errors.

while executing
"source -notrace ./.Xil/Vivado-1523-ip-10-0-59-127/realtime/toplevel_gen.tcl"
invoked from within
"synth_design -top "toplevel_gen" -part "xc7k70tfbg676-1" -flatten_hierarchy "full""
(file "/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/synthesize.tcl" line 20)
invoked from within
"source "/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/synthesize.tcl""
# exit
INFO: [Common 17-206] Exiting Vivado at Wed Mar 8 09:39:09 2017...

 

 

Any ideas?

 

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Message 1 of 5
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Hi Biebel,

 

What version of LabVIEW, and what version of the CompactRIO driver are you using? Have you been able to try compiling locally, or do you not have the Xilinx Tools for Vivado installed on your local machine?

Cheers!

TJ G
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Message 2 of 5
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Labview 2104 sp1

Labview Realtime 14.01

 

I installed the latest NI compactRio 16.1 and  I tried also the NI compactRIO 14.5 drivers which where already installed.

Locally or in the cloud, I keep getting the same error 😞

 

I've no idea which causes this errors of licensing

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Message 3 of 5
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The licensing errors aren't the cause of your problem here, its these lines:

 

ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:295]
ERROR: [Synth 8-1031] knidmahighspeedsinksize is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:296]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:301]
ERROR: [Synth 8-1031] knidmahighspeedsinkbase is not declared [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:302]
INFO: [Synth 8-2810] unit pkgshimswitchedlinkdmaportifc ignored due to previous errors [/opt/apps/NIFPGA/jobs/MWPk3JM_C103822/PkgShimSwitchedLinkDmaPortIfc.vhd:68]

 

I'm going to try to reproduce this error on my end using your SW stack. I'll let you know if I discover anything useful.

Cheers!

TJ G
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Message 4 of 5
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OK, so I set up a machine with LV 2014 SP1 & RIO 16.0, and I'm not getting the same behavior (my compilations are working fine).

 

Is there any way you can share the code that's failing to compile for you?

Can you generate and post a MAX technical report for your system so I can see if there is anything else on the software side we may be missing?

Cheers!

TJ G
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