Xilinx FFT function: how to feed values to it one at a time?

[count3r5tr1ke]

[Background info so you don't have to read the entire thread:] I am using LV2012 FPGA with the RIO Evaluation Kit (sbRIO-9636). I have a 1d array of U16 that I want to put into the Xilinx FPGA FFT function. It turns out that the array is too big to fit on the FPGA, so I have to store it on the host, transfer the values one at a time to the FPGA for processing, then the output values get sent back to the host and the graph is displayed on the host vi. In order to accomplish this, I would like to know how to set up the variables on the host VI, the RT VI, and the FPGA VI. My code is based on the sample code that came with the RIO eval kit tutorial. I would like to add two new variables, FFT Input Array and FFT Output Array. 

Here's the current FPGA vi: (need to put the array constant on the host, and put something else here)

@count3r5tr1ke wrote:

OK, I looked at that web page and I'd like to use programmatic front panel communication so I can store the array on the host and feed the values one at a time to the FPGA vi. In that case, what should replace the array constant on the FPGA vi? The rest of the variables have FPGA I/O items, but maybe the input array is different because the source of the data is the host, not the board inputs.

I created a new shared variable and called it "FFT Input Array" that I put on the RT microprocessor vi. Is this the right configuration? (other than the read/write control, I can't select the input array yet probably because it's not on the FPGA vi yet. It's hard to tell how the configuration should be, because all the other variables are going the other way (data from FPGA to host) .

Also, is this the right way to set up the host vi? The FFT input array has its own event case, while the rest of the variables are in another case.

---

[alcava.cr]

If you want to use programmatic front panel communication you will require a control/indicator of the same data type and dimension at the FPGA VI. I would recommend a different approach and use a DMA FIFO instead (see examples at the NI Example Finder). If you need to handle more data in the future this will help with the scalability of your program. FYI

[count3r5tr1ke]

Are there any examples for programmatic FPGA interface communication? That's what I want, for now. Scalability is less important than just getting some results. I don't know why the forum won't let me upload my zip file, it's only 12.5 MB. So here's a link: http://www.4shared.com/zip/de-hgXvF/New_folder__2_.html

(use the small blue download button)

This code is based on the tutorial VI, which came on the cd with the RIO evaluation kit, it has plenty of examples of variables transferring data from the FPGA to the RT to the host, but none going the other way.

[count3r5tr1ke]

I'm also trying to get my hardware and simulation working (either one, but preferably both) so I can keep working on this. I posted another thread for that if you have an opinion on that. The thread might get moved though. 

http://forums.ni.com/t5/Version-Conversion/Anyone-have-the-2012-setup-util-for-RIO-Eval-Kit-Also-que...

[count3r5tr1ke]

I've attached the current version of the project. (a little different from the pics I posted). 

[Jeff.St]

Count3r5tr1ke,

Is it necessary to use the Xilinx FFT?  It may be easier to implement the one provided by LabVIEW FPGA.  Here is a link that may help as well.

Examples for the LabVIEW FPGA FFT Function

Best,

[count3r5tr1ke]

I appreciate your links. The LV FFT only takes fixed-point, whereas Xilinx can handle single-precision float. Also, I had previously looked at the examples you cited and they use DMA. 

I'm trying to make another version of the project that has a mini version of the input array, so that the only data transfer necessary is back to the host. Hopefully that way I'd just have to troubleshoot the Xilinx IP. The host VI and RT VI have no errors,  but for the FPGA VI I get an error on the FFT Output Subarray wire and loop tunnel: "Arrays must be fixed size in current target." I did set the arrays to fixed size, and I also  selected "Autopreallocate arrays and strings" as this webpage says: http://digital.ni.com/public.nsf/allkb/83FF1EB9DA561820862574BF007C654F

I've attached this version of the project as well, cleaned up the file structure so there aren't a bunch of nested folders. 

[count3r5tr1ke]

(Discussion continued from https://decibel.ni.com/content/message/48796#48796)

I tried the "FFT with Handshaking" example, and I replaced the sine wave generator with 1/4 of my array, through a for loop to make the values one at a time. That's the only change I made (it's on the FPGA VI):

It compiles just fine, and when I run it there's no error, but it just doesn't show any result. The FFT Spectrum graph and the Signal graph are just flat at 0. Please help. 

[count3r5tr1ke]

Is it me, or does the input array go to all zeroes after compiling and running? 
I've attached a separate VI, this doesn't go into the project but it contains the array and the subarray. Run the VI if necessary, to get the subarray. (The complete array won't fit on the FPGA.) This is not an FPGA VI, I suggest opening a new project and then opening this VI, so it won't open in an FPGA project. It'll give unnecessary errors if you open it in an FPGA target. The subarray size is 320. When testing the project, please make sure the input array isn't all zeroes.

[count3r5tr1ke]

I also tried putting my input subarray into the "Windowed FFT" example (see attached). The only change I made was to add another choice to the case structure. If I'm trying to put the first value in and process it, then the next value, etc. is that the right way to do it? 

(see the image at http://i.snag.gy/NdE5p.jpg, I would insert it but the image dialog freezes up)

 I ran the VI for 6 hours so it should show something even if it is running really slow. It shows the actual frequency being the same as the frequency control (6.78k) but the graphs are still blank. I find it strange that the input graph is blank, because the dataset is built in. But the input array seems to have reset itself back to some kind of default.  

(Note: on the host VI, the top graph should be the output, and the bottom graph should be the input.)