Xilinx Coregen does not appear in palette

[NickDngc]

I would like to use Xilinx Coregen to generate FIFOs for my LabVIEW FPGA project. The help file says to look on the programming palette inside an FPGA VI, but I don't have one. I have the IP Integration Node and all the FPGA functions, but no Coregen. The application itself is installed on my computer. Is there an installation option that I missed? How can I get this to show up?

Rgds,

Nick

[Donovan_B]

The Xilinx Coregen palette is only supported on Virtex 5 targets currently.  Which device are you using?

You can still use Coregen to generate cores and then use the IP Integration Node to use them in LabVIEW, but the integrated palette is only available for Virtex 5 right now.

[NickDngc]

I'm using the Virtex 2 (PXI-7811R), so that would explain my problem.

I tried using the IP integration node, but I couldn't get that to work either. When I generated the cores, I set the device as Virtex family, device="xc2v1000", package=fg456, speed grade=-4. These are the same values I see in the Xilinx log file after generating a bitstream. I added the core (.xco) file in IP integration node and pressed "Generate". I then got the following message:

INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
   selected IP Fifo_Generator v4.4 to a more recent version.
INFO:sim:760 - You can use the CORE Generator IP upgrade flow to upgrade the
   selected IP Fifo_Generator v4.4 to a more recent version.
WARNING:encore:175 - Project options (family='virtex2', device='xc2v1000',
   package='fg456', speed grade='-4') are inconsistent, unavailable or
   incorrectly entered.
Generated IP unsuccessfully. Fix the above error(s) or warning(s) and generate the IP again.

Any idea what's going on here?

[Tim_W.]

Hi Nick,

What version of LabVIEW and FPGA are you using? The Xilinx Coregen tool should be visible as a part of the standard 2011 installation, but is not a part of the 2010 package. However, it is available as an add-on for 2010 via this link. Let me know if you're still having trouble getting it to show up.

Tim W.

Applications Engineering

National Instruments

http://www.ni.com/support 

[NickDngc]

LabVIEW 2011, FPGA Module 2011, NI-RIO 4.0, PXI-7811R

[Donovan_B]

Which version of Xilinx Coregen did you use for generating the .xco file?  Xilinx 12.4 does not support Virtex-II, which is why there are two separate installers for the Xilinx tools in LV FPGA 2011.  The compilation for a Virtex-II target must use version 10.1 of the Xilinx tools and Coregen files are generally not backwards compatible.  You will need to make sure the cores are generated in Xilinx 10.1 in order to use them on a Virtex-II.

[NickDngc]

I found exactly that problem; I started with ISE 12.4 (or whichever was the more recent) and found I couldn't even choose the correct target, so I opened the Coregen in ISE 10.1 and used that. That's when I got the message in IP Integration Node telling my config was impossible.

[Donovan_B]

For certain technical reasons, you will not be able to use the .xco file as the top-level file for the IP Integration Node when using a Virtex-II device.  You can only use VHDL source or a compiled netlist as the top-level file.

So, you will need to include a netlist synthesized in Coregen instead of just the .xco file itself.  You should then be able to include the .ngc file as the synthesis file and configure the simulation behavior to use the .vhd file generated for synthesis or use a post-synthesis model.  I generated a FIFO with version 4.4. and set the simulation behavior to include generated_fifo.vhd as the user-defined simulation model and was able to configure the IP Integration Node and perform a full compile of a LabVIEW FPGA diagram containing that node.

[NickDngc]

I'm very new to FPGAs, so please excuse the ignorance. I'm not undestanding what goes...

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@Donovan B wrote:

...

So, you will need to include a netlist synthesized in Coregen instead of just the .xco file itself.  ***HERE*** You should then be able to include the .ngc file as the synthesis file and configure the simulation behavior to use the .vhd file generated for synthesis or use a post-synthesis model.

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Is this netlist one of the files that's automatically generated in Coregen, or do I need to regenerate it with different options? As far as adding the files, would I then need to add two files (netlist file and .ngc) before Generating?

[Donovan_B · Accepted solution]

The .ngc file IS the netlist.  It should be generated next to the .xco file as part of the Coregen process.  It should have the same name (for mine I named the component generated_fifo) so you would see generated_fifo.xco, generated_fifo.ngc, and there should also be a generated_fifo.vhd.  The .xco file is essentially a list of coefficients and parameters for generating the core.  The .ngc file is a synthesized version of the core that used the .xco file for generation.  The .vhd file is a simulation model of the core.  It usually will not be synthesizable, but can be used for simulation.

So, the only file you would need to add in the configuration for the node would be the .ngc file (which is the netlist).  You will then need to configure the simulation behavior to either use the matching .vhd file for simulation or use a post-synthesis model.