Write on DMA FIFO sbRIO 9606

[Pepe727]

I have 2 FIFOs, both set up like this

One target to host and the another one host to target. My work consist in encrypt files using the target, both that isnt the problem. When I write(in host) and read the proccesed information of 10,000 bytes works fine, but when i try to encrypt files of ~25 Mb i got an error. I have observed that modifing my time loop period (i have 10 uSec) (in target vi), i can process larger files (~40k elemnts). So i have some doubts.

1) Why if my file is bigger than 2047 elemnts, works fine? and Why if my file have ~25mb doesnt work? 

2) How the loop period intervenes on my cycle?

[JensG69 · Accepted solution]

Actually the buffersize on the RT-side of the FIFOs is bigger than the buffer size on the FPGA-side, that you have configured to be 2047 elements. See e.g: http://zone.ni.com/reference/en-XX/help/371599N-01/lvfpgahost/fpga_method_fifo_config/

But of course, the buffer size is not 25 MB. So depending on how fast you empty the FIFO on the FPGA side you get 10k or even 40k elements to write, but not 25 MB, unless you define the size of the FIFOs on the RT-side to be so big.

Regards, Jens