I am happy that you pointed out the issue with my RT array indexing. I have implemented your idea, and it works well. Also, I made an additional set of code to facilitate graphing every nth value that is obtained by the FPGA. Through this, I can alter my undersampling / oversampling.
I have also fixed the frequency dependent amplitude of my readings through a different route. It occurred due to a low-pass frequency response of the oscilloscope probes that I was using. After changing the attenuation factor from 10x to 1x, the amplitudes of my signals are now correct, so it was not actually aliasing (but the RT bug was).