03-06-2009 10:46 AM
I am using a cRIO-9073 to develop a data acquisition system.
When I try to use a FIFO to pass data from the FPGA to the host, I get extremely long compile times (hours!!).
I am using only one analog input from a 9205 module at present in my FPGA loop.
Is there some explication to that?
Thanks for any help you can provide.
Michel
Solved! Go to Solution.
03-06-2009 01:26 PM
Michel, how much RAM do you have in your system? FIFOs do add a decent amount of under-the-hood bits to the FPGA, and maybe it pushed it past the memory limit where the compiler starts temporarily storing data on disk. This can make compiles run for an order of magnitude longer. Adding the FIFO may have pushed you over that limit. Having at least a gig of RAM will definitely make life better for compiling.
03-06-2009 02:07 PM
Paul,
Thanks for your reply.
I finally found the problem: the FIFO size I had requested in the FIFO's properties was too big at 32K elements times 4 (for U32 data type of the FIFO). It was filling the FPGA 128K RAM completely, leaving no flexibility for the compiler for the remaining logic. Too bad there was no warning message for that!
By reducing the size of my FIFO to 4K, the compile time came back to around 5-10 minutes instead of hours!
Michel Lanthier
03-06-2009 05:50 PM
03-08-2009 09:19 AM
Jim,
The problem was not the amount of memory in my PC (I do have 1G or RAM in my PC). The problem was the size of the FIFO which would not fit in the FPGA. The solution was to reduce the size of the FIFO.
I did not think the goal of this forum was to be a race to get the most KUDOS and ACCEPTED SOLUTION tags but rather to help everybody solve their problems as efficiently as possible.
Regards,
Michel
03-08-2009 08:11 PM - edited 03-08-2009 08:13 PM
The goal is most certainly not to get the most KUDOS and ACCEPTED SOLUTIONS, but they sure are nice.
I understand that I missed the solution, though. Sorry.