Dear All, I am happy to report that by replacing the IO Module\Data Clock with 200MHz. Clock in the FPGA VI I have been able to get successful compilation. I am enclosing the screentshot of the compilation status window. Apparently it was the clock problem which was giving me the error. The hint provided by WishKebab was very helpful. I am grateful to you all. I will now create Host VI and follow rest of the steps in NI 5782R user Manual and Specifications (page 15) and if I face any other problem then I will contact you again. Thanks once more. Kamal
