I think you are talking about "Timed Loops" which are "Single Cycle Timed Loops" on FPGA.
As FPGA is meant to run as long as it is powered, a software "Stop" doesnt make much sense.
You are correct, Norbert, it is a timed loop. I am used to seeing single cycle timed loops with a 'TRUE' constant wired to the stop. Guess it is not necessary.