What is the reason why DIO pins in NI-MyRio cannot be used after using DIO pins in NI-FPGA?

[constructionworker]

Hello everyone

In the code I use any DIO pin on the FPGA target and then toggle the DIO pin on and off via Myrio, that works. No problem here. Also, I'm using a different pin than the one used in the FPGA and I can't turn the DIO pin on-off in Myrio with Express VI.
What is the reason of this? I could solve this problem by programming all the DIO pins directly through the FPGA and then just triggering those pins through myrio.
But still I wonder. Does it prevent toolkits in Myrio from reaching the FPGA I/O pins because the FPGA automatically deploys it to run after it's programmed?

Any opinion given is worthy of respect.

[Bob_Schor]

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@constructionworker wrote:

Any opinion given is worthy of respect.

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Here is an opinion you've been given numerous times -- for an explanation of why your code does precisely what you tell it to do (rather than what you want it to do), you need to show us respect by posting your code.  Please.

Bob Schor

[constructionworker]

Sorry, the code is attached.I thought it wasn't necessary.What I want to do here is to use DIO pins on both FPGA and Myrio.

[Bob_Schor]

Thank you -- looking at your code, I think I may be able to shed some light on your issue.

The myRIO can function on two levels (particularly when running LabVIEW 2018, with the addition of the myRIO Software Toolkit, which provides you with the Express VIs you are using).  One level, meant to get you started with the really sophisticated Real-Time hardware in the myRIO, is to use the myRIO Toolkit, and the sub-VIs and Express VIs you can find in the "myRIO" Block Diagram sub-Palette.  Most of this Toolkit consists of Express VIs, which "hides the messy details" involved in communicating with the myRIO's FPGA (which has access to the I/O Ports) and "wraps" access to the hardware in a layer of Software.

You have mixed the "high-level" (Express VI) code with some "low-level" (FPGA) code.  I must confess that I've not used the Express VIs very much, so I'm not sure what you'd need to do to convince the Express VI to only access a single DIO channel.  

Your FPGA code is very easy to understand -- however you set the Open-close pin control, that value will not be changed by the Express VI (because every 25 ns, the value is reset to match the value passed in via the Open-close pin Control).

My advice would be to go with either a "pure" Toolkit solution (using Express VIs) or a "pure" FPGA solution.

Bob Schor

[constructionworker]

Thank you for your explanation.
I have now solved the problem using pure FPGA, but I wonder why it cannot be done. Does it prevent Express VIs from running while the FPGA code is running?

[Bob_Schor]

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@constructionworker wrote:

I have now solved the problem using pure FPGA, but I wonder why it cannot be done. Does it prevent Express VIs from running while the FPGA code is running?

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While I haven't exactly tried this, it would not surprise me if you could, say, use the Analog Input Express VI along with a custom FPGA that manipulated some DIO pins (as these two use different myRIO "resources").  

Bob Schor