One (1) 9503 on a cRIO-9030 takes up:
Total Slices: 47.8% (6361 out of 13300)
Slice Registers: 15.5% (16504 out of 106400)
Slice LUTs: 34.5% (18364 out of 53200)
Block RAMs: 5.0% (7 out of 140)
DSP48s: 4.5% (10 out of 220
If I add two (2) more 9503 modules, will I run out of slices? Has anyone tried three modules on a 9030?
As per my understanding, number of slices, LUTs, etc. occupied, depends on the final code compliled on FPGA side; not on cRIO module, what is gonna to be used with cRIO controller...
But I can be wrong, and there are some minimal requirements of resources what one should consider...
You posted this roughly 24hrs ago. You'd have had your answer ~23 hours ago if you had made a quick dummy project.
We have no idea what you're doing in your FPGA VI. You cannot get a reasonable answer here but you certainly could get the answer for yourself in a quick fashion
Based on the results you had above it looks like it might be tight but it is not a straightforward question.
Once the FPGA gets full the compiler will add more levels of optimisation. As yours is only half full it may not have fully optimised the code so just because one uses 47% does not necessarily mean 3 won't fit.
The only way to be sure is to add 3 in a project and attempt a compile. You don't have to have the hardware for the compile so you can confirm if it will work or not.
After posting I did make a project with three (3) NI 9503s on a 9030.
I used the example: LabVIEW 2016\examples\motion\Primitives\HW\9503 Torque Smoothing\9503 Stepper Drive (Torque Smoothing Coeff).lvproj
It barely fits, results:
Total Slices: 94.4% (9678 out of 10250)
Slice Registers: 31.7% (25986 out of 82000)
Slice LUTs: 75.8% (31082 out of 41000)
Block RAMs: 4.4% (6 out of 135)
DSP48s: 13.8% (33 out of 240)
I recompiled with a space optimization setting in the build spec but the numbers looked similar.
The reason I posted a question that could be 'answered' by just making a project and doing a test compile is that this is a waste of time if I could leverage someone else's experience. Also, do I need to make this for all the cRIO/FPGA options to figure out the minimum?
Maybe NI or someone else had experience with this module and the example. We are spec'ing out hardware for a new project, the solution may get productized, so the smaller the cRIO used the better.
In the past (with the power modules for cRIO) there were IEC power module packages that NI had put together that required a minimum size FPGA to function. The customer went with a smaller cRIO/FPGA and we ended up having to rework the FPGA project to fit the smaller FPGA.
We are spec'ing out hardware for a new project, the solution may get productized, so the smaller the cRIO used the better.
Such questions should be discussed with your local NI representative!
When they can't answer directly they will ask NI support using your exact specs…
We can make some estimated guesses based on the reports but the only way to be certain is to try the compiles. What I can tell you from experience:
I'm afraid this is more of an art than a science when you are pushing the borders due to the compiler optimisations. The other thing is you can optimise code - you could perhaps look at that code and identify where you might be able to use registers to reduce the LUT requirement - though that can get tricky. Hopefully that explains some of what you are seeing though and offers some guidance.