LabVIEW

cancel
Showing results for 
Search instead for 
Did you mean: 

What is the minimum cRIO controller that can fit the FPGA logic of three (3) NI 9503 modules?

One (1) 9503 on a cRIO-9030 takes up:

Total Slices: 47.8% (6361 out of 13300)
Slice Registers: 15.5% (16504 out of 106400)
Slice LUTs: 34.5% (18364 out of 53200)
Block RAMs: 5.0% (7 out of 140)
DSP48s: 4.5% (10 out of 220

 

If I add two (2) more 9503 modules, will I run out of slices?  Has anyone tried three modules on a 9030?


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
0 Kudos
Message 1 of 7
(1,832 Views)

As per my understanding, number of slices, LUTs, etc. occupied, depends on the final code compliled on FPGA side; not on cRIO module, what is gonna to be used with cRIO controller...

But I can be wrong, and there are some minimal requirements of resources what one should consider...

 

logos_middle.jpg

0 Kudos
Message 2 of 7
(1,783 Views)

You posted this roughly 24hrs ago.  You'd have had your answer ~23 hours ago if you had made a quick dummy project. 

 

We have no idea what you're doing in your FPGA VI.  You cannot get a reasonable answer here but you certainly could get the answer for yourself in a quick fashion

0 Kudos
Message 3 of 7
(1,760 Views)

Based on the results you had above it looks like it might be tight but it is not a straightforward question.

 

Once the FPGA gets full the compiler will add more levels of optimisation. As yours is only half full it may not have fully optimised the code so just because one uses 47% does not necessarily mean 3 won't fit.

 

The only way to be sure is to add 3 in a project and attempt a compile. You don't have to have the hardware for the compile so you can confirm if it will work or not.


 

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
0 Kudos
Message 4 of 7
(1,748 Views)

After posting I did make a project with three (3) NI 9503s on a 9030.

I used the example: LabVIEW 2016\examples\motion\Primitives\HW\9503 Torque Smoothing\9503 Stepper Drive (Torque Smoothing Coeff).lvproj

 

It barely fits, results:

Total Slices: 94.4% (9678 out of 10250)
Slice Registers: 31.7% (25986 out of 82000)
Slice LUTs: 75.8% (31082 out of 41000)
Block RAMs: 4.4% (6 out of 135)
DSP48s: 13.8% (33 out of 240)

 

I recompiled with a space optimization setting in the build spec but the numbers looked similar.

 

The reason I posted a question that could be 'answered' by just making a project and doing a test compile is that this is a waste of time if I could leverage someone else's experience.  Also, do I need to make this for all the cRIO/FPGA options to figure out the minimum?

 

Maybe NI or someone else had experience with this module and the example.  We are spec'ing out hardware for a new project, the solution may get productized, so the smaller the cRIO used the better.

 

In the past (with the power modules for cRIO) there were IEC power module packages that NI had put together that required a minimum size FPGA to function.  The customer went with a smaller cRIO/FPGA and we ended up having to rework the FPGA project to fit the smaller FPGA.


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
0 Kudos
Message 5 of 7
(1,735 Views)

Hi Terry,

 

We are spec'ing out hardware for a new project, the solution may get productized, so the smaller the cRIO used the better.

Such questions should be discussed with your local NI representative!

When they can't answer directly they will ask NI support using your exact specs…

Best regards,
GerdW


using LV2020 on Win8.1+cRIO
0 Kudos
Message 6 of 7
(1,731 Views)

Hi Terry,

 

We can make some estimated guesses based on the reports but the only way to be certain is to try the compiles. What I can tell you from experience:

 

  • BlockRAMs and DSPs don't really vary. If your algorithm needs 48 DSPs then that is what it needs unless you optimise the algorithm to need less (there are probably some exceptions where the compiler may be able to use slices instead but I find this to be a good rule of thumb).
  • It's important to realise that a slice is a component made of registers and LUTs. Exactly how much depends on the family of FPGAs. The kintex 7 family has 4x 6-input LUTs and 8x registers per slice. The space optimisation is how much the design crams into these slices.
  • In your original design you see that the total slices percentage is much higher than either of the registers or the LUTs. This means it hasn't optimised for space much - lots of slices have only LUTs used, lots of slices have only registers used.
  • With 3 9503s you can see those values are now much closer. 75% of LUTs are used to 94% of slices. 
  • At this point you could start to look at the required number of LUTs and registers to compare different FPGA slices as a rough rule of thumb rather than just compiling but it all depends on the FPGA optimisation as to how far that can be pushed.
  • Looking where this sits beware the Zync targets though - they have similar counts but I'm fairly sure some of the space is used by NI as part of the compliation as well.

I'm afraid this is more of an art than a science when you are pushing the borders due to the compiler optimisations. The other thing is you can optimise code - you could perhaps look at that code and identify where you might be able to use registers to reduce the LUT requirement - though that can get tricky. Hopefully that explains some of what you are seeing though and offers some guidance.

James Mc
========
CLA and cRIO Fanatic
My writings on LabVIEW Development are at devs.wiresmithtech.com
0 Kudos
Message 7 of 7
(1,727 Views)