What is the exact clock rate on the FPGA?

[cermf]

What is the exact clock rate of the the FPGA in a compactRIO system? I mean clock rate as defined by how many ticks the "Tick Count" VI increases in one second. At first I thought it is identical to the FPGA onboard clock rate, 40Mhz in my case. But then, the compilation report always gives a "requested clock rate"  which is not 40 Mhz but 41.67Mhz for my VI (see the attached timing report). For my application, I need to derive an exact time in seconds from the tick count VI.

Does anybody know, what exactly the compilation report means by "requested clock rate"? The Labview help says: "Requested (MHz)—Indicates the clock rate, in megahertz, at which the FPGA VI or FPGA VI component must be able to run." That doesn't make much sense to me. Does the onboard clock rate speed up a bit? Does the VI create its own derived clock and actually runs with 41.67Mhz? And what does the "Tick Count VI" use?

If anybody count point me in the right direction, that would be wonderful.

[GerdW]

Hi cermf,

it's more like: RequestedMHz means to clock rate required to run the code. It has to be smaller than the MaximumMHz value.

The clock rate still stays at 40MHz. I just wonder why the RequestedValue is higher than 40MHz and still the compilation completes...

[cermf]

Hi GerdW,

Thanks for the answer. The VI does indeed run with the expected output rates. So, does Labview set up a derived clock with 41.67Mhz(num=25; denum=24) and runs the VI with it? Then again, what clock does the "Tick Count" VI refer to?

Questions upon questions....

[Wetzer · Accepted solution]

Hello cermf,

The Tick Count VI will refer to 40MHz Clock assuming that you dont use it within another timing domain.

To cope with Clock inaccuracys LabVIEW FPGA requests a slightly higher clock rate to compile with.

There is no derived Clock created here, the VI will use a 40Mhz Clock.

Regards,

Moritz M.

[cermf]

Confirmed, the top-level VI uses a 40Mhz clock; the tick count was measured to increases by 40 million ticks/s.

It is not clear to me how requesting a higher rates can alleviate clock inaccuracies, or what a timing domain is. But these are technical details as long as I understand what the VIs are doing that I use.

Thank you!

[K.Waris]

Hello Cermf

You could indeed use tick count vi to benchmark with your code in while loop to find the exact time taken by your code to execute on FPGA target. A good practice is to use wait until next ms multiple function in a flat sequence. Add frame to the right of the frame containing wait until next ms multiple function. Put all your code in this second frame. Whatever value you wire to the left input of wait until next ms multiple function will determine the execution rate of your code. If you are using C series modules then rate of execution of your code is determined by conversion time (in case of analog input modules) of the modules which could be found in data sheets.

Requested clock is pretty much saying : I want to get to Birmingham in half an hour so get me a car which is faster and could get me there in half an hour, so the taxi service sends you a car which is fast enough to take you there in 25 minutes but driver will not drive fast if he knows that he could get there in half an hour.

Hope it helps