LabVIEW
What is myRIO high throughput math used for?
A SCTL is indeed tied to the configured clock rate for this loop. Everything inside the SCTL must be able to execute within a single clock cycle and the FPGA compiler will check that that is the case.
Each logic function has some delay as the electrical signal passes from the input to the output an the combination of all the logic circuits that form a path inside the loop have a combined execution time that is the sum of all those delays in the longest path. The compiler knows what delay each logic function has, calculates all the delays for each individual path and makes sure that the longest such path takes less time than a single cycle has. If it finds that even one single logic path violates this timing constraint by as much as a fraction of a nano second, the compilation fails with a timing constraint error.
The normal math functions are not programmed to have a constant execution time, and especially floating point math requires the use of internal loops whose execution time can vary depending on the values to process. Such code cannot be precalculate in terms of exact execution time, since it will depend on the actual numeric value at runtime, how long the calculation will take. Therefore inclusion of these nodes in a SCTL is not allowed as the timing constraint of the SCTL might be violated at runtime without a sure and reasonable way to determine that at compile time.
The high throughput math functions are implemented in a way that is efficient to include in the FPGA fabric and deterministic too, and their execution time is short although they often use pipelining to perform the operation in a very short timeslot. Pipelining however does require the loop to execute several times before the result from one input arrives at the output, but it still processes one new value in every iteration, there simply is an inherent delay for the reaction to a specific input stimulus.
@ExactPlace441 wrote:
Hello rolfk,
This explanation of the High Throughput Math functions in regards to the delays associated with their computations makes sense.
It seems to me that the High Throughput Math functions are able to convey to the FPGA SCTL how long they will take to compute beforehand. Thus, the FPGA knows whether it will be able to fit it in the clock cycle. For normal math functions, however, different inputs can result in different computation times, and the FPGA SCTL doesn't like that ambiguity. Is this correct?
For a technical discussion this is a bit a vague definition but for the purpose of explaining it to a non-technician this is fairly accurate.
As to your other question you asked before, I really don't understand what you try to say there. It doesn't depend if the data comes from a DMA FIFO or a digital or analog IO. The data rate, if you take one sample per iteration (this isn't a strict requirement I have loops that run at a higher rate and only process one sample every 4th iteration for instance, and other loops that process two or more samples in parallel per iteration) is whatever the loop interval produces. A loop running at 40MHz and processing one sample per iteration will obviously have a datarate of 40M Samples per second, not 1 (what?) as you state.
