Watchdog in cRIO system

[run happy]

Hello,

I need to implement watchdog programming in my cRIO control system. Where is the proper location to place the logic? Within the FPGA VI like the WD-Poling-cRIO.lvproj example or within the Host VI using the available RT Wathdog VI’s?

Staci

[gsussman]

The only real place that there is a hardware watchdog outside of the software environment is on the RT controller.

If you are trying to detect the widest range of system faults, the hardware WDT would be the way to go.

To tie that into the operation with your FPGA component, if you have any data coming back from the FPGA (FIFO?), you could set up your "whack" logic to ensure that data must be received from the FPGA (no timeout) in order for the whack to occur. This would ensure that both the RT and FPGA software was operating for a successful WDT whack to occur.

In the event that one or the other parts of the system goes out to lunch, the whack would not be executed and the cRIO would reboot.