Want to replace a large shift register with a FIFO

[jasonhill]

When you say FIFO, I think queue.  I jiggered around with the logic a tiny bit.  More to make it clear for myself than anything else.  Both case structures are the identical.  I show one in each state.

Message Edited by jasonhill on 06-27-2006 03:09 PM

[Nige K]

Hi again,

Many thanks for the above example of queues...  I am currently trying this out but unfortunately as always appears to be the case with this work because I am using the 7811R FPGA card these functions do not appear on the pallette instead there is only the FPGA FIFO read and write icons.  I assume it is still possible to do the above with these but as I say I am still working on it.

I reply to the previous question the hardware that I am compiling this all on is the NI-8187 embedded system which runs windows XP with a 2.5GHz cpu and I think 256Mb of RAM.

When previously using the large arrays which would run through the compilation would produce errors due to overmapping of slices etc - again I assume this is due to them physically being to big for the 7811R card, hopefully using the FPGA FIFO write and read commands willl allow me to effectively produce much larger arrays/queues.

Again any more info is very much appreciated as I am learning a lot doing what I initally (and foolishly) thought would be a trivial task!

Thanks again

Nigel

[jasonhill]

I am so sorry Nigel.  I completely missed the FPGA issue.  I don't have that module and really don't know how the FIFO differes from queues.  Seems my "help" is not all that helpful. 

[Nige K]

No worries - my preliminary attempts look hopeful so I think it should be possible, I just need to get the timing of the writes and reads sorted I think I may be there!

Finger crossed,

Nigel

[Nige K]

As stated above my preliminary attempts did look hopeful but once again I have hit a bit of a brick wall.  I have managed to incorporate the FPGA FIFO write and read but I think there is a conflict between them as things are not quite working as I would expect...

I have attached my VI and a screen dump of it and would like to ask a couple of questions relating to it.  First how can I make sure the write and reads exxecute in the correct order, would a flat sequence structure be best.  I have tried using the error terminals to force the sequence but this slowed the loop execution down too much.

Which brings me onto my second point; can anybody see any ways in which this VI could be made more efficient and therefore execute faster as at present I can compile at 80MHz which is great as I want the loop to execute once every 50ns.  Unfortunately when timing the loop it is actually taking approximately 10 ticks per loop i.e. 125ns.  I have tried the single cycle timed loop but it would not compile and generated several errors.

Again, any help is greatly appreciated,

Nigel

[Stuart_R]

Hi Nigel,

Firstly, moving away from the use of arrays was a good idea, as these will waste the slices you have available and the problems you were seeing demonstrate this. The new approach is far better.

Have you tried using a flat sequence structure in order to make the write/read sequential and if so, what effect did it have? Is there any way that you could separate out some of the code into multiple loops?

Can you give me more of a description on what you are trying to implement and what the FIFO are being used for as this will help me understand better.

It may also be possible to pipeline some of your code so that the write/read operations doen't occur sequentially (this will add in an obvious delay), but in parallel.

Check out the following links:
Pipelining and optimisation:
http://zone.ni.com/devzone/conceptd.nsf/webmain/10ff44f70a213a068625706500745350

LabVIEW 8.0 training (I know you are using 7.1 but a lot of the concept material still holds true, see the last slide show):
http://zone.ni.com/devzone/conceptd.nsf/webmain/62B388DB80B557028625703700639B89


Hope this helps, but do let me know more info so I can help you further!

Thanks,

Stuart

[John Rich]

Nigel,

I don't quite understand what you're trying to do with the FIFO.  If you write to the FIFO and then read from the FIFO in the same loop then you're not accomplishing anything, you could just as well pass the data through on a wire.  You should set your FIFO up so that you're writing in one loop and reading in a parallel loop.  You can use the Empty terminal to determine whether code is executed in the read loop.  You can also use the Full terminal from to generate an error if the read loop is lagging behind the write loop.

A more detailed description of what you're trying to accomplish would be useful.  Perhaps you don't need the FIFO or the big shift register.  If you're just wanting to count the number of boolean crossings for various amounts of time (iterations of the loop) then you could set up a SR for each amount of time and use the Remainder from the Quotient and Remainder function to determine the interval at which to reset the counter (x is the value from the iteration terminal and y is the number of iterations for the time cycle).

I found your use of the > function to find the boolean crossing rather interesting.  I had not thought of that (actually, I didn't even know that the > function would take a boolean input).

[Nige K]

Thanks for your comments,  Stuart, yes I have just tried using a flat sequence structure to force the sequential read writes and this does appear to work but unfortunately slows the loop execution down further to approximately 25ticks or 312.5ns which is too slow for my application as the pulses I wih to measure are 100ns wide i.e. I need the loop to run at 20MHz.  Your suggestion of separating the code into multiple loops is next on my list - actually it is the only thing left on my list...

For both your information and for John's (thanks for your comments as well) I will attempt to describe what I am attempting to achieve.  I have attached a block diagramof the circuit that I am trying to replicate.  In this the pulses are read into the "shift register" which is say 32microsecond in length and as each pulse enters it increments a scalar and when the pulses leave the "shift register" they decrement this scalar.  Therefore the scalar keeps a running total of the total number of pulses contained within the "shift register" at any time.  I wish to count the correlations between each pulse i.e. if a pulse enters the "shift register" while one is already in it the total correlations is 1 then if a third enters the total correlations is 3 and so on as shown below.

number of events in shift register          number of recorded correlations

0, 1, 2, 3, 4, n                                         0, 0, 1, 3, 6 n(n-1)/2 

I believe I have managed to replicate this part by using a FIFO which is initialised by filling with zeros to effectively produce a queue of data.

In addition to using the prompt incoming pulses to dump the value contained in the "shift register" I also want to delay the incoming pulses by approximately 1milli second and use this to produce a second indicator shown as the accidentals in the circuit diagram.  Again I have replicated this through the use of another FIFO which has a much larger depth than the other and therefore I think acts like a longer data queue.

I hope this sheds some light on what I am trying to do, this circuit is commonly used in counting neutrons and determining correlations between incident neutrons.

Many thanks again,

Nigel